- if (i.suffix == WORD_OPCODE_SUFFIX) {
- if (i.prefixes == MAX_PREFIXES) {
- as_bad("%d prefixes given and 'w' opcode suffix gives too many prefixes",
- MAX_PREFIXES);
- return;
- }
- i.prefix[i.prefixes++] = WORD_PREFIX_OPCODE;
- }
- }
-
- /* For insns with operands there are more diddles to do to the opcode. */
- if (i.operands) {
- /* If we found a reverse match we must alter the opcode direction bit
- found_reverse_match holds bit to set (different for int &
- float insns). */
-
- if (found_reverse_match) {
- t->base_opcode |= found_reverse_match;
- }
-
- /*
- The imul $imm, %reg instruction is converted into
- imul $imm, %reg, %reg. */
- if (t->opcode_modifier & imulKludge) {
- i.regs[2] = i.regs[1]; /* Pretend we saw the 3 operand case. */
- i.reg_operands = 2;
- }
-
- /* Certain instructions expect the destination to be in the i.rm.reg
- field. This is by far the exceptional case. For these instructions,
- if the source operand is a register, we must reverse the i.rm.reg
- and i.rm.regmem fields. We accomplish this by faking that the
- two register operands were given in the reverse order. */
- if ((t->opcode_modifier & ReverseRegRegmem) && i.reg_operands == 2) {
- unsigned int first_reg_operand = (i.types[0] & Reg) ? 0 : 1;
- unsigned int second_reg_operand = first_reg_operand + 1;
- reg_entry *tmp = i.regs[first_reg_operand];
- i.regs[first_reg_operand] = i.regs[second_reg_operand];
- i.regs[second_reg_operand] = tmp;
- }
-
- if (t->opcode_modifier & ShortForm) {
- /* The register or float register operand is in operand 0 or 1. */
- unsigned int o = (i.types[0] & (Reg|FloatReg)) ? 0 : 1;
- /* Register goes in low 3 bits of opcode. */
- t->base_opcode |= i.regs[o]->reg_num;
- } else if (t->opcode_modifier & ShortFormW) {
- /* Short form with 0x8 width bit. Register is always dest. operand */
- t->base_opcode |= i.regs[1]->reg_num;
- if (i.suffix == WORD_OPCODE_SUFFIX ||
- i.suffix == DWORD_OPCODE_SUFFIX)
- t->base_opcode |= 0x8;
- } else if (t->opcode_modifier & Seg2ShortForm) {
- if (t->base_opcode == POP_SEG_SHORT && i.regs[0]->reg_num == 1) {
- as_bad("you can't 'pop cs' on the 386.");
- return;
- }
- t->base_opcode |= (i.regs[0]->reg_num << 3);
- } else if (t->opcode_modifier & Seg3ShortForm) {
- /* 'push %fs' is 0x0fa0; 'pop %fs' is 0x0fa1.
- 'push %gs' is 0x0fa8; 'pop %fs' is 0x0fa9.
- So, only if i.regs[0]->reg_num == 5 (%gs) do we need
- to change the opcode. */
- if (i.regs[0]->reg_num == 5)
- t->base_opcode |= 0x08;
- } else if (t->opcode_modifier & Modrm) {
- /* The opcode is completed (modulo t->extension_opcode which must
- be put into the modrm byte.
- Now, we make the modrm & index base bytes based on all the info
- we've collected. */
-
- /* i.reg_operands MUST be the number of real register operands;
- implicit registers do not count. */
- if (i.reg_operands == 2) {
- unsigned int source, dest;
- source = (i.types[0] & (Reg|SReg2|SReg3|Control|Debug|Test)) ? 0 : 1;
- dest = source + 1;
- i.rm.mode = 3;
- /* We must be careful to make sure that all segment/control/test/
- debug registers go into the i.rm.reg field (despite the whether
- they are source or destination operands). */
- if (i.regs[dest]->reg_type & (SReg2|SReg3|Control|Debug|Test)) {
- i.rm.reg = i.regs[dest]->reg_num;
- i.rm.regmem = i.regs[source]->reg_num;
- } else {
- i.rm.reg = i.regs[source]->reg_num;
- i.rm.regmem = i.regs[dest]->reg_num;
- }
- } else { /* if it's not 2 reg operands... */
- if (i.mem_operands) {
- unsigned int fake_zero_displacement = 0;
- unsigned int o = (i.types[0] & Mem) ? 0 : ((i.types[1] & Mem) ? 1 : 2);
-
- /* Encode memory operand into modrm byte and base index byte. */
-
- if (i.base_reg == esp && ! i.index_reg) {
- /* <disp>(%esp) becomes two byte modrm with no index register. */
- i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
- i.rm.mode = mode_from_disp_size(i.types[o]);
- i.bi.base = ESP_REG_NUM;
- i.bi.index = NO_INDEX_REGISTER;
- i.bi.scale = 0; /* Must be zero! */
- } else if (i.base_reg == ebp && !i.index_reg) {
- if (! (i.types[o] & Disp)) {
- /* Must fake a zero byte displacement.
- There is no direct way to code '(%ebp)' directly. */
- fake_zero_displacement = 1;
- /* fake_zero_displacement code does not set this. */
- i.types[o] |= Disp8;
- }
- i.rm.mode = mode_from_disp_size(i.types[o]);
- i.rm.regmem = EBP_REG_NUM;
- } else if (! i.base_reg && (i.types[o] & BaseIndex)) {
- /* There are three cases here.
- Case 1: '<32bit disp>(,1)' -- indirect absolute.
- (Same as cases 2 & 3 with NO index register)
- Case 2: <32bit disp> (,<index>) -- no base register with disp
- Case 3: (, <index>) --- no base register;
- no disp (must add 32bit 0 disp). */
- i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
- i.rm.mode = 0; /* 32bit mode */
- i.bi.base = NO_BASE_REGISTER;
- i.types[o] &= ~Disp;
- i.types[o] |= Disp32; /* Must be 32bit! */
- if (i.index_reg) { /* case 2 or case 3 */
- i.bi.index = i.index_reg->reg_num;
- i.bi.scale = i.log2_scale_factor;
- if (i.disp_operands == 0)
- fake_zero_displacement = 1; /* case 3 */
- } else {
- i.bi.index = NO_INDEX_REGISTER;
- i.bi.scale = 0;
- }
- } else if (i.disp_operands && !i.base_reg && !i.index_reg) {
- /* Operand is just <32bit disp> */
- i.rm.regmem = EBP_REG_NUM;
- i.rm.mode = 0;
- i.types[o] &= ~Disp;
- i.types[o] |= Disp32;
- } else {
- /* It's not a special case; rev'em up. */
- i.rm.regmem = i.base_reg->reg_num;
- i.rm.mode = mode_from_disp_size(i.types[o]);
- if (i.index_reg) {
- i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
- i.bi.base = i.base_reg->reg_num;
- i.bi.index = i.index_reg->reg_num;
- i.bi.scale = i.log2_scale_factor;
- if (i.base_reg == ebp && i.disp_operands == 0) { /* pace */
- fake_zero_displacement = 1;
- i.types[o] |= Disp8;
- i.rm.mode = mode_from_disp_size(i.types[o]);
- }
- }
- }
- if (fake_zero_displacement) {
- /* Fakes a zero displacement assuming that i.types[o] holds
- the correct displacement size. */
- exp = &disp_expressions[i.disp_operands++];
- i.disps[o] = exp;
- exp->X_seg = SEG_ABSOLUTE;
- exp->X_add_number = 0;
- exp->X_add_symbol = (symbolS *) 0;
- exp->X_subtract_symbol = (symbolS *) 0;
- }
-
- /* Select the correct segment for the memory operand. */
- if (i.seg) {
- unsigned int seg_index;
- const seg_entry *default_seg;
-
- if (i.rm.regmem == ESCAPE_TO_TWO_BYTE_ADDRESSING) {
- seg_index = (i.rm.mode<<3) | i.bi.base;
- default_seg = two_byte_segment_defaults[seg_index];
- } else {
- seg_index = (i.rm.mode<<3) | i.rm.regmem;
- default_seg = one_byte_segment_defaults[seg_index];
- }
- /* If the specified segment is not the default, use an
- opcode prefix to select it */
- if (i.seg != default_seg) {
- if (i.prefixes == MAX_PREFIXES) {
- as_bad("%d prefixes given and %s segment override gives too many prefixes",
- MAX_PREFIXES, i.seg->seg_name);
- return;
- }
- i.prefix[i.prefixes++] = i.seg->seg_prefix;
- }
- }
- }
-
- /* Fill in i.rm.reg or i.rm.regmem field with register operand
- (if any) based on t->extension_opcode. Again, we must be careful
- to make sure that segment/control/debug/test registers are coded
- into the i.rm.reg field. */
- if (i.reg_operands) {
- unsigned int o =
- (i.types[0] & (Reg|SReg2|SReg3|Control|Debug|Test)) ? 0 :
- (i.types[1] & (Reg|SReg2|SReg3|Control|Debug|Test)) ? 1 : 2;
- /* If there is an extension opcode to put here, the register number
- must be put into the regmem field. */
- if (t->extension_opcode != None)
- i.rm.regmem = i.regs[o]->reg_num;
- else i.rm.reg = i.regs[o]->reg_num;
-
- /* Now, if no memory operand has set i.rm.mode = 0, 1, 2
- we must set it to 3 to indicate this is a register operand
- int the regmem field */
- if (! i.mem_operands) i.rm.mode = 3;
- }
-
- /* Fill in i.rm.reg field with extension opcode (if any). */
- if (t->extension_opcode != None)
- i.rm.reg = t->extension_opcode;
- }
- }
- }
- }
-
- /* Handle conversion of 'int $3' --> special int3 insn. */
- if (t->base_opcode == INT_OPCODE && i.imms[0]->X_add_number == 3) {
- t->base_opcode = INT3_OPCODE;
- i.imm_operands = 0;
- }
-
- /* We are ready to output the insn. */
- {
- register char * p;
-
- /* Output jumps. */
- if (t->opcode_modifier & Jump) {
- int n = i.disps[0]->X_add_number;
-
- switch (i.disps[0]->X_seg) {
- case SEG_ABSOLUTE:
- if (fits_in_signed_byte(n)) {
- p = frag_more (2);
- p[0] = t->base_opcode;
- p[1] = n;
-#if 0 /* leave out 16 bit jumps - pace */
- } else if (fits_in_signed_word(n)) {
- p = frag_more (4);
- p[0] = WORD_PREFIX_OPCODE;
- p[1] = t->base_opcode;
- md_number_to_chars (&p[2], n, 2);
-#endif
- } else { /* It's an absolute dword displacement. */
- if (t->base_opcode == JUMP_PC_RELATIVE) { /* pace */
- /* unconditional jump */
- p = frag_more (5);
- p[0] = 0xe9;
- md_number_to_chars (&p[1], n, 4);
- } else {
- /* conditional jump */
- p = frag_more (6);
- p[0] = TWO_BYTE_OPCODE_ESCAPE;
- p[1] = t->base_opcode + 0x10;
- md_number_to_chars (&p[2], n, 4);
- }
- }
- break;
- default:
- /* It's a symbol; end frag & setup for relax.
- Make sure there are 6 chars left in the current frag; if not
- we'll have to start a new one. */
- /* I caught it failing with obstack_room == 6,
- so I changed to <= pace */
- if (obstack_room (&frags) <= 6) {
- frag_wane(frag_now);
- frag_new (0);
- }
- p = frag_more (1);
- p[0] = t->base_opcode;
- frag_var (rs_machine_dependent,
- 6, /* 2 opcode/prefix + 4 displacement */
- 1,
- ((unsigned char) *p == JUMP_PC_RELATIVE
- ? ENCODE_RELAX_STATE (UNCOND_JUMP, BYTE)
- : ENCODE_RELAX_STATE (COND_JUMP, BYTE)),
- i.disps[0]->X_add_symbol,
- n, p);
- break;
- }
- } else if (t->opcode_modifier & (JumpByte|JumpDword)) {
- int size = (t->opcode_modifier & JumpByte) ? 1 : 4;
- int n = i.disps[0]->X_add_number;
-
- if (fits_in_unsigned_byte(t->base_opcode)) {
- FRAG_APPEND_1_CHAR (t->base_opcode);
- } else {
- p = frag_more (2); /* opcode can be at most two bytes */
- /* put out high byte first: can't use md_number_to_chars! */
- *p++ = (t->base_opcode >> 8) & 0xff;
- *p = t->base_opcode & 0xff;
- }
-
- p = frag_more (size);
- switch (i.disps[0]->X_seg) {
- case SEG_ABSOLUTE:
- md_number_to_chars (p, n, size);
- if (size == 1 && ! fits_in_signed_byte(n)) {
- as_bad("loop/jecx only takes byte displacement; %d shortened to %d",
- n, *p);
- }
- break;
- default:
- fix_new (frag_now, p - frag_now->fr_literal, size,
- i.disps[0]->X_add_symbol, i.disps[0]->X_subtract_symbol,
- i.disps[0]->X_add_number, 1, NO_RELOC);
- break;
- }
- } else if (t->opcode_modifier & JumpInterSegment) {
- p = frag_more (1 + 2 + 4); /* 1 opcode; 2 segment; 4 offset */
- p[0] = t->base_opcode;
- if (i.imms[1]->X_seg == SEG_ABSOLUTE)
- md_number_to_chars (p + 1, i.imms[1]->X_add_number, 4);
+ if ((i.suffix == WORD_OPCODE_SUFFIX) ^ flag_16bit_code)
+ {
+ if (! check_prefix (WORD_PREFIX_OPCODE))
+ return;
+ i.prefix[i.prefixes++] = WORD_PREFIX_OPCODE;
+ }
+ }
+
+ /* For insns with operands there are more diddles to do to the opcode. */
+ if (i.operands)
+ {
+ /* Default segment register this instruction will use
+ for memory accesses. 0 means unknown.
+ This is only for optimizing out unnecessary segment overrides. */
+ const seg_entry *default_seg = 0;
+
+ /* True if this instruction uses a memory addressing mode,
+ and therefore may need an address-size prefix. */
+ int uses_mem_addrmode = 0;
+
+
+ /* If we found a reverse match we must alter the opcode direction bit
+ found_reverse_match holds bit to set (different for int &
+ float insns). */
+
+ i.tm.base_opcode ^= found_reverse_match;
+
+ /* The imul $imm, %reg instruction is converted into
+ imul $imm, %reg, %reg, and the clr %reg instruction
+ is converted into xor %reg, %reg. */
+ if (i.tm.opcode_modifier & regKludge)
+ {
+ unsigned int first_reg_op = (i.types[0] & Reg) ? 0 : 1;
+ /* Pretend we saw the extra register operand. */
+ i.regs[first_reg_op+1] = i.regs[first_reg_op];
+ i.reg_operands = 2;
+ }
+
+ if (i.tm.opcode_modifier & ShortForm)
+ {
+ /* The register or float register operand is in operand 0 or 1. */
+ unsigned int op = (i.types[0] & (Reg | FloatReg)) ? 0 : 1;
+ /* Register goes in low 3 bits of opcode. */
+ i.tm.base_opcode |= i.regs[op]->reg_num;
+ }
+ else if (i.tm.opcode_modifier & ShortFormW)
+ {
+ /* Short form with 0x8 width bit. Register is always dest. operand */
+ i.tm.base_opcode |= i.regs[1]->reg_num;
+ if (i.suffix == WORD_OPCODE_SUFFIX ||
+ i.suffix == DWORD_OPCODE_SUFFIX)
+ i.tm.base_opcode |= 0x8;
+ }
+ else if (i.tm.opcode_modifier & Modrm)
+ {
+ /* The opcode is completed (modulo i.tm.extension_opcode which
+ must be put into the modrm byte).
+ Now, we make the modrm & index base bytes based on all the
+ info we've collected. */
+
+ /* i.reg_operands MUST be the number of real register operands;
+ implicit registers do not count. */
+ if (i.reg_operands == 2)
+ {
+ unsigned int source, dest;
+ source = ((i.types[0]
+ & (Reg
+ | SReg2
+ | SReg3
+ | Control
+ | Debug
+ | Test
+ | RegMMX))
+ ? 0 : 1);
+ dest = source + 1;
+
+ /* Certain instructions expect the destination to be
+ in the i.rm.reg field. This is by far the
+ exceptional case. For these instructions, if the
+ source operand is a register, we must reverse the
+ i.rm.reg and i.rm.regmem fields. We accomplish
+ this by pretending that the two register operands
+ were given in the reverse order. */
+ if (i.tm.opcode_modifier & ReverseRegRegmem)
+ {
+ reg_entry *tmp = i.regs[source];
+ i.regs[source] = i.regs[dest];
+ i.regs[dest] = tmp;
+ }
+
+ i.rm.mode = 3;
+ /* We must be careful to make sure that all
+ segment/control/test/debug/MMX registers go into
+ the i.rm.reg field (despite whether they are
+ source or destination operands). */
+ if (i.regs[dest]->reg_type
+ & (SReg2 | SReg3 | Control | Debug | Test | RegMMX))
+ {
+ i.rm.reg = i.regs[dest]->reg_num;
+ i.rm.regmem = i.regs[source]->reg_num;
+ }
+ else
+ {
+ i.rm.reg = i.regs[source]->reg_num;
+ i.rm.regmem = i.regs[dest]->reg_num;
+ }
+ }
+ else
+ { /* if it's not 2 reg operands... */
+ if (i.mem_operands)
+ {
+ unsigned int fake_zero_displacement = 0;
+ unsigned int op = ((i.types[0] & Mem)
+ ? 0
+ : (i.types[1] & Mem) ? 1 : 2);
+
+ /* Encode memory operand into modrm byte and base index
+ byte. */
+
+ if (i.base_reg == esp && !i.index_reg)
+ {
+ /* <disp>(%esp) becomes two byte modrm with no index
+ register. */
+ i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
+ i.rm.mode = mode_from_disp_size (i.types[op]);
+ i.bi.base = ESP_REG_NUM;
+ i.bi.index = NO_INDEX_REGISTER;
+ i.bi.scale = 0; /* Must be zero! */
+ }
+ else if (i.base_reg == ebp && !i.index_reg)
+ {
+ if (!(i.types[op] & Disp))
+ {
+ /* Must fake a zero byte displacement. There is
+ no direct way to code '(%ebp)' directly. */
+ fake_zero_displacement = 1;
+ /* fake_zero_displacement code does not set this. */
+ i.types[op] |= Disp8;
+ }
+ i.rm.mode = mode_from_disp_size (i.types[op]);
+ i.rm.regmem = EBP_REG_NUM;
+ }
+ else if (!i.base_reg && (i.types[op] & BaseIndex))
+ {
+ /* There are three cases here.
+ Case 1: '<32bit disp>(,1)' -- indirect absolute.
+ (Same as cases 2 & 3 with NO index register)
+ Case 2: <32bit disp> (,<index>) -- no base register with disp
+ Case 3: (, <index>) --- no base register;
+ no disp (must add 32bit 0 disp). */
+ i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
+ i.rm.mode = 0; /* 32bit mode */
+ i.bi.base = NO_BASE_REGISTER;
+ i.types[op] &= ~Disp;
+ i.types[op] |= Disp32; /* Must be 32bit! */
+ if (i.index_reg)
+ { /* case 2 or case 3 */
+ i.bi.index = i.index_reg->reg_num;
+ i.bi.scale = i.log2_scale_factor;
+ if (i.disp_operands == 0)
+ fake_zero_displacement = 1; /* case 3 */
+ }
+ else
+ {
+ i.bi.index = NO_INDEX_REGISTER;
+ i.bi.scale = 0;
+ }
+ }
+ else if (i.disp_operands && !i.base_reg && !i.index_reg)
+ {
+ /* Operand is just <32bit disp> */
+ i.rm.regmem = EBP_REG_NUM;
+ i.rm.mode = 0;
+ i.types[op] &= ~Disp;
+ i.types[op] |= Disp32;
+ }
+ else
+ {
+ /* It's not a special case; rev'em up. */
+ i.rm.regmem = i.base_reg->reg_num;
+ i.rm.mode = mode_from_disp_size (i.types[op]);
+ if (i.index_reg)
+ {
+ i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
+ i.bi.base = i.base_reg->reg_num;
+ i.bi.index = i.index_reg->reg_num;
+ i.bi.scale = i.log2_scale_factor;
+ if (i.base_reg == ebp && i.disp_operands == 0)
+ { /* pace */
+ fake_zero_displacement = 1;
+ i.types[op] |= Disp8;
+ i.rm.mode = mode_from_disp_size (i.types[op]);
+ }
+ }
+ }
+ if (fake_zero_displacement)
+ {
+ /* Fakes a zero displacement assuming that i.types[op]
+ holds the correct displacement size. */
+ exp = &disp_expressions[i.disp_operands++];
+ i.disps[op] = exp;
+ exp->X_op = O_constant;
+ exp->X_add_number = 0;
+ exp->X_add_symbol = (symbolS *) 0;
+ exp->X_op_symbol = (symbolS *) 0;
+ }
+
+ /* Find the default segment for the memory operand.
+ Used to optimize out explicit segment specifications. */
+ if (i.seg[0])
+ {
+ unsigned int seg_index;
+
+ if (i.rm.regmem == ESCAPE_TO_TWO_BYTE_ADDRESSING)
+ {
+ seg_index = (i.rm.mode << 3) | i.bi.base;
+ default_seg = two_byte_segment_defaults[seg_index];
+ }