-/* Prefixes will be emitted in the order defined below.
- WAIT_PREFIX must be the first prefix since FWAIT is really is an
- instruction, and so must come before any prefixes.
- The preferred prefix order is SEG_PREFIX, ADDR_PREFIX, DATA_PREFIX,
- LOCKREP_PREFIX. */
-#define WAIT_PREFIX 0
-#define SEG_PREFIX 1
-#define ADDR_PREFIX 2
-#define DATA_PREFIX 3
-#define LOCKREP_PREFIX 4
-#define REX_PREFIX 5 /* must come last. */
-#define MAX_PREFIXES 6 /* max prefixes per opcode */
-
-/* we define the syntax here (modulo base,index,scale syntax) */
-#define REGISTER_PREFIX '%'
-#define IMMEDIATE_PREFIX '$'
-#define ABSOLUTE_PREFIX '*'
-
-/* these are the instruction mnemonic suffixes. */
-#define WORD_MNEM_SUFFIX 'w'
-#define BYTE_MNEM_SUFFIX 'b'
-#define SHORT_MNEM_SUFFIX 's'
-#define LONG_MNEM_SUFFIX 'l'
-#define QWORD_MNEM_SUFFIX 'q'
-/* Intel Syntax. Use a non-ascii letter since since it never appears
- in instructions. */
-#define LONG_DOUBLE_MNEM_SUFFIX '\1'
-
-#define END_OF_INSN '\0'
-
-/*
- 'templates' is for grouping together 'template' structures for opcodes
- of the same name. This is only used for storing the insns in the grand
- ole hash table of insns.
- The templates themselves start at START and range up to (but not including)
- END.
- */
-typedef struct
-{
- const template *start;
- const template *end;
-}
-templates;
-
-/* 386 operand encoding bytes: see 386 book for details of this. */
-typedef struct
-{
- unsigned int regmem; /* codes register or memory operand */
- unsigned int reg; /* codes register operand (or extended opcode) */
- unsigned int mode; /* how to interpret regmem & reg */
-}
-modrm_byte;
-
-/* x86-64 extension prefix. */
-typedef int rex_byte;
-
-/* The SSE5 instructions have a two bit instruction modifier (OC) that
- is stored in two separate bytes in the instruction. Pick apart OC
- into the 2 separate bits for instruction. */
-#define DREX_OC0(x) (((x) & 1) != 0)
-#define DREX_OC1(x) (((x) & 2) != 0)
-
-#define DREX_OC0_MASK (1 << 3) /* set OC0 in byte 4 */
-#define DREX_OC1_MASK (1 << 2) /* set OC1 in byte 3 */
-
-/* OC mappings */
-#define DREX_XMEM_X1_X2_X2 0 /* 4 op insn, dest = src3, src1 = reg/mem */
-#define DREX_X1_XMEM_X2_X2 1 /* 4 op insn, dest = src3, src2 = reg/mem */
-#define DREX_X1_XMEM_X2_X1 2 /* 4 op insn, dest = src1, src2 = reg/mem */
-#define DREX_X1_X2_XMEM_X1 3 /* 4 op insn, dest = src1, src3 = reg/mem */
-
-#define DREX_XMEM_X1_X2 0 /* 3 op insn, src1 = reg/mem */
-#define DREX_X1_XMEM_X2 1 /* 3 op insn, src1 = reg/mem */
-
-/* Information needed to create the DREX byte in SSE5 instructions. */
-typedef struct
-{
- unsigned int reg; /* register */
- unsigned int rex; /* REX flags */
- unsigned int modrm_reg; /* which arg goes in the modrm.reg field */
- unsigned int modrm_regmem; /* which arg goes in the modrm.regmem field */
-} drex_byte;
-
-/* 386 opcode byte to code indirect addressing. */
-typedef struct
-{
- unsigned base;
- unsigned index;
- unsigned scale;
-}
-sib_byte;
-
-enum processor_type
-{
- PROCESSOR_UNKNOWN,
- PROCESSOR_I386,
- PROCESSOR_I486,
- PROCESSOR_PENTIUM,
- PROCESSOR_PENTIUMPRO,
- PROCESSOR_PENTIUM4,
- PROCESSOR_NOCONA,
- PROCESSOR_CORE,
- PROCESSOR_CORE2,
- PROCESSOR_K6,
- PROCESSOR_ATHLON,
- PROCESSOR_K8,
- PROCESSOR_GENERIC32,
- PROCESSOR_GENERIC64,
- PROCESSOR_AMDFAM10
-};
-
-/* x86 arch names, types and features */
-typedef struct
-{
- const char *name; /* arch name */
- enum processor_type type; /* arch type */
- i386_cpu_flags flags; /* cpu feature flags */
-}
-arch_entry;
-