- if (! (S_GET_SEGMENT(fixp->fx_addsy)->flags & SEC_MERGE))
- return 0;
- if (strncmp (S_GET_SEGMENT (fixp->fx_addsy)->name, ".debug", 6) == 0)
- return 0;
-
- return 1;
-}
-
-/* Insert an operand value into an instruction. */
-
-static void
-mn10300_insert_operand (insnp, extensionp, operand, val, file, line, shift)
- unsigned long *insnp;
- unsigned long *extensionp;
- const struct mn10300_operand *operand;
- offsetT val;
- char *file;
- unsigned int line;
- unsigned int shift;
-{
- /* No need to check 32bit operands for a bit. Note that
- MN10300_OPERAND_SPLIT is an implicit 32bit operand. */
- if (operand->bits != 32
- && (operand->flags & MN10300_OPERAND_SPLIT) == 0)
- {
- long min, max;
- offsetT test;
- int bits;
-
- bits = operand->bits;
- if (operand->flags & MN10300_OPERAND_24BIT)
- bits = 24;
-
- if ((operand->flags & MN10300_OPERAND_SIGNED) != 0)
- {
- max = (1 << (bits - 1)) - 1;
- min = - (1 << (bits - 1));
- }
- else
- {
- max = (1 << bits) - 1;
- min = 0;
- }
-
- test = val;
-
- if (test < (offsetT) min || test > (offsetT) max)
- as_warn_value_out_of_range (_("operand"), test, (offsetT) min, (offsetT) max, file, line);
- }
-
- if ((operand->flags & MN10300_OPERAND_SPLIT) != 0)
- {
- *insnp |= (val >> (32 - operand->bits)) & ((1 << operand->bits) - 1);
- *extensionp |= ((val & ((1 << (32 - operand->bits)) - 1))
- << operand->shift);
- }
- else if ((operand->flags & MN10300_OPERAND_24BIT) != 0)
- {
- *insnp |= (val >> (24 - operand->bits)) & ((1 << operand->bits) - 1);
- *extensionp |= ((val & ((1 << (24 - operand->bits)) - 1))
- << operand->shift);
- }
- else if ((operand->flags & (MN10300_OPERAND_FSREG | MN10300_OPERAND_FDREG)))
- {
- /* See devo/opcodes/m10300-opc.c just before #define FSM0 for an
- explanation of these variables. Note that FMT-implied shifts
- are not taken into account for FP registers. */
- unsigned long mask_low, mask_high;
- int shl_low, shr_high, shl_high;
-
- switch (operand->bits)
- {
- case 5:
- /* Handle regular FP registers. */
- if (operand->shift >= 0)
- {
- /* This is an `m' register. */
- shl_low = operand->shift;
- shl_high = 8 + (8 & shl_low) + (shl_low & 4) / 4;
- }
- else
- {
- /* This is an `n' register. */
- shl_low = -operand->shift;
- shl_high = shl_low / 4;
- }
-
- mask_low = 0x0f;
- mask_high = 0x10;
- shr_high = 4;
- break;
-
- case 3:
- /* Handle accumulators. */
- shl_low = -operand->shift;
- shl_high = 0;
- mask_low = 0x03;
- mask_high = 0x04;
- shr_high = 2;
- break;
-
- default:
- abort ();
- }
- *insnp |= ((((val & mask_high) >> shr_high) << shl_high)
- | ((val & mask_low) << shl_low));
- }
- else if ((operand->flags & MN10300_OPERAND_EXTENDED) == 0)
- {
- *insnp |= (((long) val & ((1 << operand->bits) - 1))
- << (operand->shift + shift));
-
- if ((operand->flags & MN10300_OPERAND_REPEATED) != 0)
- *insnp |= (((long) val & ((1 << operand->bits) - 1))
- << (operand->shift + shift + operand->bits));
- }
- else
- {
- *extensionp |= (((long) val & ((1 << operand->bits) - 1))
- << (operand->shift + shift));
-
- if ((operand->flags & MN10300_OPERAND_REPEATED) != 0)
- *extensionp |= (((long) val & ((1 << operand->bits) - 1))
- << (operand->shift + shift + operand->bits));
- }
-}
-
-static unsigned long
-check_operand (insn, operand, val)
- unsigned long insn ATTRIBUTE_UNUSED;
- const struct mn10300_operand *operand;
- offsetT val;
-{
- /* No need to check 32bit operands for a bit. Note that
- MN10300_OPERAND_SPLIT is an implicit 32bit operand. */
- if (operand->bits != 32
- && (operand->flags & MN10300_OPERAND_SPLIT) == 0)
- {
- long min, max;
- offsetT test;
- int bits;
-
- bits = operand->bits;
- if (operand->flags & MN10300_OPERAND_24BIT)
- bits = 24;
-
- if ((operand->flags & MN10300_OPERAND_SIGNED) != 0)
- {
- max = (1 << (bits - 1)) - 1;
- min = - (1 << (bits - 1));
- }
- else
- {
- max = (1 << bits) - 1;
- min = 0;
- }