+ const char * name;
+ unsigned int length;
+ unsigned int bitfield;
+ } erratas[] =
+ {
+ { STRING_COMMA_LEN ("cpu4"), SILICON_ERRATA_CPU4 },
+ { STRING_COMMA_LEN ("cpu8"), SILICON_ERRATA_CPU8 },
+ { STRING_COMMA_LEN ("cpu11"), SILICON_ERRATA_CPU11 },
+ { STRING_COMMA_LEN ("cpu12"), SILICON_ERRATA_CPU12 },
+ { STRING_COMMA_LEN ("cpu13"), SILICON_ERRATA_CPU13 },
+ { STRING_COMMA_LEN ("cpu19"), SILICON_ERRATA_CPU19 },
+ };
+
+ do
+ {
+ for (i = ARRAY_SIZE (erratas); i--;)
+ if (strncasecmp (arg, erratas[i].name, erratas[i].length) == 0)
+ {
+ if (c == OPTION_SILICON_ERRATA)
+ silicon_errata_fix |= erratas[i].bitfield;
+ else
+ silicon_errata_warn |= erratas[i].bitfield;
+ arg += erratas[i].length;
+ break;
+ }
+ if (i < 0)
+ {
+ as_warn (_("Unrecognised CPU errata name starting here: %s"), arg);
+ break;
+ }
+ if (*arg == 0)
+ break;
+ if (*arg != ',')
+ as_warn (_("Expecting comma after CPU errata name, not: %s"), arg);
+ else
+ arg ++;
+ }
+ while (*arg != 0);
+ }
+ return 1;
+
+ case OPTION_MMCU:
+ if (arg == NULL)
+ as_fatal (_("MCU option requires a name\n"));
+
+ if (strcasecmp ("msp430", arg) == 0)
+ selected_isa = MSP_ISA_430;
+ else if (strcasecmp ("msp430xv2", arg) == 0)
+ selected_isa = MSP_ISA_430Xv2;
+ else if (strcasecmp ("msp430x", arg) == 0)
+ selected_isa = MSP_ISA_430X;
+ else
+ {
+ int i;
+
+ for (i = ARRAY_SIZE (msp430_mcu_data); i--;)
+ if (strcasecmp (msp430_mcu_data[i].name, arg) == 0)
+ {
+ switch (msp430_mcu_data[i].revision)
+ {
+ case 0: selected_isa = MSP_ISA_430; break;
+ case 1: selected_isa = MSP_ISA_430X; break;
+ case 2: selected_isa = MSP_ISA_430Xv2; break;
+ }
+ break;
+ }
+ }
+ /* It is not an error if we do not match the MCU name. */
+ return 1;
+
+ case OPTION_MCPU:
+ if (strcmp (arg, "430") == 0
+ || strcasecmp (arg, "msp430") == 0)
+ selected_isa = MSP_ISA_430;
+ else if (strcasecmp (arg, "430x") == 0
+ || strcasecmp (arg, "msp430x") == 0)
+ selected_isa = MSP_ISA_430X;
+ else if (strcasecmp (arg, "430xv2") == 0
+ || strcasecmp (arg, "msp430xv2") == 0)
+ selected_isa = MSP_ISA_430Xv2;
+ else
+ as_fatal (_("unrecognised argument to -mcpu option '%s'"), arg);
+ return 1;
+
+ case OPTION_RELAX:
+ msp430_enable_relax = 1;
+ return 1;
+
+ case OPTION_POLYMORPHS:
+ msp430_enable_polys = 1;
+ return 1;
+
+ case OPTION_LARGE:
+ large_model = TRUE;
+ return 1;
+
+ case OPTION_NO_INTR_NOPS:
+ gen_interrupt_nops = FALSE;
+ return 1;
+ case OPTION_INTR_NOPS:
+ gen_interrupt_nops = TRUE;
+ return 1;
+
+ case OPTION_WARN_INTR_NOPS:
+ warn_interrupt_nops = TRUE;
+ return 1;
+ case OPTION_NO_WARN_INTR_NOPS:
+ warn_interrupt_nops = FALSE;
+ return 1;
+
+ case OPTION_UNKNOWN_INTR_NOPS:
+ do_unknown_interrupt_nops = TRUE;
+ return 1;
+ case OPTION_NO_UNKNOWN_INTR_NOPS:
+ do_unknown_interrupt_nops = FALSE;
+ return 1;
+
+ case OPTION_MOVE_DATA:
+ move_data = TRUE;
+ return 1;
+
+ case OPTION_DATA_REGION:
+ if (strcmp (arg, "upper") == 0
+ || strcmp (arg, "either") == 0)
+ upper_data_region_in_use = TRUE;
+ if (strcmp (arg, "upper") == 0
+ || strcmp (arg, "either") == 0
+ /* With data-region=none, the compiler has generated code assuming
+ data could be in the upper region, but nothing has been explicitly
+ placed there. */
+ || strcmp (arg, "none") == 0)
+ lower_data_region_only = FALSE;
+ return 1;
+ }
+
+ return 0;
+}
+
+/* The intention here is to have the mere presence of these sections
+ cause the object to have a reference to a well-known symbol. This
+ reference pulls in the bits of the runtime (crt0) that initialize
+ these sections. Thus, for example, the startup code to call
+ memset() to initialize .bss will only be linked in when there is a
+ non-empty .bss section. Otherwise, the call would exist but have a
+ zero length parameter, which is a waste of memory and cycles.
+
+ The code which initializes these sections should have a global
+ label for these symbols, and should be marked with KEEP() in the
+ linker script. */
+
+static void
+msp430_make_init_symbols (const char * name)
+{
+ if (strncmp (name, ".bss", 4) == 0
+ || strncmp (name, ".lower.bss", 10) == 0
+ || strncmp (name, ".either.bss", 11) == 0
+ || strncmp (name, ".gnu.linkonce.b.", 16) == 0)
+ (void) symbol_find_or_make ("__crt0_init_bss");
+
+ if (strncmp (name, ".data", 5) == 0
+ || strncmp (name, ".lower.data", 11) == 0
+ || strncmp (name, ".either.data", 12) == 0
+ || strncmp (name, ".gnu.linkonce.d.", 16) == 0)
+ (void) symbol_find_or_make ("__crt0_movedata");
+ /* Note - data assigned to the .either.data section may end up being
+ placed in the .upper.data section if the .lower.data section is
+ full. Hence the need to define the crt0 symbol.
+ The linker may create upper or either data sections, even when none exist
+ at the moment, so use the value of the data-region flag to determine if
+ the symbol is needed. */
+ if (strncmp (name, ".either.data", 12) == 0
+ || strncmp (name, ".upper.data", 11) == 0
+ || upper_data_region_in_use)
+ (void) symbol_find_or_make ("__crt0_move_highdata");
+
+ /* See note about .either.data above. */
+ if (strncmp (name, ".upper.bss", 10) == 0
+ || strncmp (name, ".either.bss", 11) == 0
+ || upper_data_region_in_use)
+ (void) symbol_find_or_make ("__crt0_init_highbss");
+
+ /* The following symbols are for the crt0 functions that run through
+ the different .*_array sections and call the functions placed there.
+ - init_array stores global static C++ constructors to run before main.
+ - preinit_array is not expected to ever be used for MSP430.
+ GCC only places initialization functions for runtime "sanitizers"
+ (i.e. {a,l,t,u}san) and "virtual table verification" in preinit_array.
+ - fini_array stores global static C++ destructors to run after calling
+ exit() or returning from main.
+ __crt0_run_array is required to actually call the functions in the above
+ arrays. */
+ if (strncmp (name, ".init_array", 11) == 0)
+ {
+ (void) symbol_find_or_make ("__crt0_run_init_array");
+ (void) symbol_find_or_make ("__crt0_run_array");
+ }
+ else if (strncmp (name, ".preinit_array", 14) == 0)
+ {
+ (void) symbol_find_or_make ("__crt0_run_preinit_array");
+ (void) symbol_find_or_make ("__crt0_run_array");
+ }
+ else if (strncmp (name, ".fini_array", 11) == 0)
+ {
+ (void) symbol_find_or_make ("__crt0_run_fini_array");
+ (void) symbol_find_or_make ("__crt0_run_array");
+ }
+}
+
+static void
+msp430_section (int arg)
+{
+ char * saved_ilp = input_line_pointer;
+ const char * name = obj_elf_section_name ();
+
+ msp430_make_init_symbols (name);
+
+ input_line_pointer = saved_ilp;
+ obj_elf_section (arg);
+}
+
+void
+msp430_frob_section (asection *sec)
+{
+ const char *name = sec->name;
+
+ if (sec->size == 0)
+ return;
+
+ msp430_make_init_symbols (name);
+}
+
+static void
+msp430_lcomm (int ignore ATTRIBUTE_UNUSED)
+{
+ symbolS *symbolP = s_comm_internal (0, s_lcomm_internal);
+
+ if (symbolP)
+ symbol_get_bfdsym (symbolP)->flags |= BSF_OBJECT;
+ (void) symbol_find_or_make ("__crt0_init_bss");
+}
+
+static void
+msp430_comm (int needs_align)
+{
+ s_comm_internal (needs_align, elf_common_parse);
+ (void) symbol_find_or_make ("__crt0_init_bss");
+}
+
+static void
+msp430_refsym (int arg ATTRIBUTE_UNUSED)
+{
+ char sym_name[1024];
+ input_line_pointer = extract_word (input_line_pointer, sym_name, 1024);
+
+ (void) symbol_find_or_make (sym_name);
+}
+
+/* Handle a .mspabi_attribute or .gnu_attribute directive.
+ attr_type is 0 for .mspabi_attribute or 1 for .gnu_attribute.
+ This is only used for validating the attributes in the assembly file against
+ the options gas has been invoked with. If the attributes and options are
+ compatible then we add the attributes to the assembly file in
+ msp430_md_end. */
+static void
+msp430_object_attribute (int attr_type)
+{
+ char tag_name_s[32];
+ char tag_value_s[32];
+ int tag_name, tag_value;
+ /* First operand is the tag name, second is the tag value e.g.
+ ".mspabi_attribute 4, 2". */
+ input_line_pointer = extract_operand (input_line_pointer, tag_name_s, 32);
+ input_line_pointer = extract_operand (input_line_pointer, tag_value_s, 32);
+ tag_name = atoi (tag_name_s);
+ tag_value = atoi (tag_value_s);
+ /* If the attribute directive is present, the tag_value should never be set
+ to 0. */
+ if (tag_name == 0 || tag_value == 0)
+ as_bad (_("bad arguments \"%s\" and/or \"%s\" in %s directive"),
+ tag_name_s, tag_value_s, (attr_type ? ".gnu_attribute"
+ : ".mspabi_attribute"));
+ else if (attr_type == 0)
+ /* Handle .mspabi_attribute. */
+ switch (tag_name)
+ {
+ case OFBA_MSPABI_Tag_ISA:
+ switch (tag_value)
+ {
+ case OFBA_MSPABI_Val_ISA_MSP430:
+ if (target_is_430x ())
+ as_bad (_("file was compiled for the 430 ISA but the %s ISA is "
+ "selected"), (target_is_430xv2 () ? "430X" : "430Xv2"));
+ break;
+ case OFBA_MSPABI_Val_ISA_MSP430X:
+ if (!target_is_430x ())
+ as_bad (_("file was compiled for the 430X ISA but the 430 ISA is "
+ "selected"));
+ break;
+ default:
+ as_bad (_("unknown MSPABI build attribute value '%d' for "
+ "OFBA_MSPABI_Tag_ISA(%d) in .mspabi_attribute directive"),
+ tag_value, OFBA_MSPABI_Tag_ISA);
+ break;
+ }
+ break;
+ case OFBA_MSPABI_Tag_Code_Model:
+ /* Fall through. */
+ case OFBA_MSPABI_Tag_Data_Model:
+ /* FIXME: Might we want to set the memory model to large if the assembly
+ file has the large model attribute, but -ml has not been passed? */
+ switch (tag_value)
+ {
+ case OFBA_MSPABI_Val_Code_Model_SMALL:
+ if (large_model)
+ as_bad (_("file was compiled for the small memory model, but the "
+ "large memory model is selected"));
+ break;
+ case OFBA_MSPABI_Val_Code_Model_LARGE:
+ if (!large_model)
+ as_bad (_("file was compiled for the large memory model, "
+ "but the small memory model is selected"));
+ break;
+ default:
+ as_bad (_("unknown MSPABI build attribute value '%d' for %s(%d) "
+ "in .mspabi_attribute directive"), tag_value,
+ (tag_name == OFBA_MSPABI_Tag_Code_Model
+ ? "OFBA_MSPABI_Tag_Code_Model"
+ : "OFBA_MSPABI_Tag_Data_Model"),
+ (tag_name == OFBA_MSPABI_Tag_Code_Model
+ ? OFBA_MSPABI_Tag_Code_Model
+ : OFBA_MSPABI_Tag_Data_Model));
+ break;
+ }
+ break;
+ default:
+ as_bad (_("unknown MSPABI build attribute tag '%d' in "
+ ".mspabi_attribute directive"), tag_name);
+ break;
+ }
+ else if (attr_type == 1)
+ /* Handle .gnu_attribute. */
+ switch (tag_name)
+ {
+ case Tag_GNU_MSP430_Data_Region:
+ /* This attribute is only applicable in the large memory model. */
+ if (!large_model)
+ break;
+ switch (tag_value)
+ {
+ case Val_GNU_MSP430_Data_Region_Lower:
+ if (!lower_data_region_only)
+ as_bad (_("file was compiled assuming all data will be in the "
+ "lower memory region, but the upper region is in use"));
+ break;
+ case Val_GNU_MSP430_Data_Region_Any:
+ if (lower_data_region_only)
+ as_bad (_("file was compiled assuming data could be in the upper "
+ "memory region, but the lower data region is "
+ "exclusively in use"));
+ break;
+ default:
+ as_bad (_("unknown GNU build attribute value '%d' for "
+ "Tag_GNU_MSP430_Data_Region(%d) in .gnu_attribute "
+ "directive"), tag_value, Tag_GNU_MSP430_Data_Region);
+ }
+ }
+ else
+ as_bad (_("internal: unexpected argument '%d' to msp430_object_attribute"),
+ attr_type);
+}
+
+const pseudo_typeS md_pseudo_table[] =
+{
+ {"arch", msp430_set_arch, OPTION_MMCU},
+ {"cpu", msp430_set_arch, OPTION_MCPU},
+ {"profiler", msp430_profiler, 0},
+ {"section", msp430_section, 0},
+ {"section.s", msp430_section, 0},
+ {"sect", msp430_section, 0},
+ {"sect.s", msp430_section, 0},
+ {"pushsection", msp430_section, 1},
+ {"refsym", msp430_refsym, 0},
+ {"comm", msp430_comm, 0},
+ {"lcomm", msp430_lcomm, 0},
+ {"mspabi_attribute", msp430_object_attribute, 0},
+ {"gnu_attribute", msp430_object_attribute, 1},
+ {NULL, NULL, 0}
+};
+
+const char *md_shortopts = "mm:,mP,mQ,ml,mN,mn,my,mY,mu,mU";
+
+struct option md_longopts[] =
+{
+ {"msilicon-errata", required_argument, NULL, OPTION_SILICON_ERRATA},
+ {"msilicon-errata-warn", required_argument, NULL, OPTION_SILICON_ERRATA_WARN},
+ {"mmcu", required_argument, NULL, OPTION_MMCU},
+ {"mcpu", required_argument, NULL, OPTION_MCPU},
+ {"mP", no_argument, NULL, OPTION_POLYMORPHS},
+ {"mQ", no_argument, NULL, OPTION_RELAX},
+ {"ml", no_argument, NULL, OPTION_LARGE},
+ {"mN", no_argument, NULL, OPTION_NO_INTR_NOPS},
+ {"mn", no_argument, NULL, OPTION_INTR_NOPS},
+ {"mY", no_argument, NULL, OPTION_NO_WARN_INTR_NOPS},
+ {"my", no_argument, NULL, OPTION_WARN_INTR_NOPS},
+ {"mu", no_argument, NULL, OPTION_UNKNOWN_INTR_NOPS},
+ {"mU", no_argument, NULL, OPTION_NO_UNKNOWN_INTR_NOPS},
+ {"md", no_argument, NULL, OPTION_MOVE_DATA},
+ {"mdata-region", required_argument, NULL, OPTION_DATA_REGION},
+ {NULL, no_argument, NULL, 0}
+};
+
+size_t md_longopts_size = sizeof (md_longopts);
+
+void
+md_show_usage (FILE * stream)
+{
+ fprintf (stream,
+ _("MSP430 options:\n"
+ " -mmcu=<msp430-name> - select microcontroller type\n"
+ " -mcpu={430|430x|430xv2} - select microcontroller architecture\n"));
+ fprintf (stream,
+ _(" -msilicon-errata=<name>[,<name>...] - enable fixups for silicon errata\n"
+ " -msilicon-errata-warn=<name>[,<name>...] - warn when a fixup might be needed\n"
+ " supported errata names: cpu4, cpu8, cpu11, cpu12, cpu13, cpu19\n"));
+ fprintf (stream,
+ _(" -mQ - enable relaxation at assembly time. DANGEROUS!\n"
+ " -mP - enable polymorph instructions\n"));
+ fprintf (stream,
+ _(" -ml - enable large code model\n"));
+ fprintf (stream,
+ _(" -mN - do not insert NOPs after changing interrupts (default)\n"));
+ fprintf (stream,
+ _(" -mn - insert a NOP after changing interrupts\n"));
+ fprintf (stream,
+ _(" -mY - do not warn about missing NOPs after changing interrupts\n"));
+ fprintf (stream,
+ _(" -my - warn about missing NOPs after changing interrupts (default)\n"));
+ fprintf (stream,
+ _(" -mU - for an instruction which changes interrupt state, but where it is not\n"
+ " known how the state is changed, do not warn/insert NOPs\n"));
+ fprintf (stream,
+ _(" -mu - for an instruction which changes interrupt state, but where it is not\n"
+ " known how the state is changed, warn/insert NOPs (default)\n"
+ " -mn and/or -my are required for this to have any effect\n"));
+ fprintf (stream,
+ _(" -md - Force copying of data from ROM to RAM at startup\n"));
+ fprintf (stream,
+ _(" -mdata-region={none|lower|upper|either} - select region data will be\n"
+ " placed in.\n"));
+}
+
+symbolS *
+md_undefined_symbol (char * name ATTRIBUTE_UNUSED)
+{
+ return NULL;
+}
+
+static char *
+extract_cmd (char * from, char * to, int limit)
+{
+ int size = 0;
+
+ while (*from && ! ISSPACE (*from) && *from != '.' && limit > size)
+ {
+ *(to + size) = *from;
+ from++;
+ size++;
+ }
+
+ *(to + size) = 0;
+
+ return from;
+}
+
+const char *
+md_atof (int type, char * litP, int * sizeP)
+{
+ return ieee_md_atof (type, litP, sizeP, FALSE);
+}
+
+void
+md_begin (void)
+{
+ struct msp430_opcode_s * opcode;
+ msp430_hash = hash_new ();
+
+ for (opcode = msp430_opcodes; opcode->name; opcode++)
+ hash_insert (msp430_hash, opcode->name, (char *) opcode);
+
+ bfd_set_arch_mach (stdoutput, TARGET_ARCH,
+ target_is_430x () ? bfd_mach_msp430x : bfd_mach_msp11);
+
+ /* Set linkrelax here to avoid fixups in most sections. */
+ linkrelax = 1;
+}
+
+static inline bfd_boolean
+is_regname_end (char c)
+{
+ return (c == 0 || ! ISALNUM (c));
+}
+
+/* Returns the register number equivalent to the string T.
+ Returns -1 if there is no such register.
+ Skips a leading 'r' or 'R' character if there is one.
+ Handles the register aliases PC and SP. */
+
+static signed int
+check_reg (char * t)
+{
+ char * endt;
+ signed long int val;
+
+ if (t == NULL || t[0] == 0)
+ return -1;
+
+ if (*t == 'r' || *t == 'R')
+ ++t;
+
+ if (strncasecmp (t, "pc", 2) == 0 && is_regname_end (t[2]))
+ return 0;
+
+ if (strncasecmp (t, "sp", 2) == 0 && is_regname_end (t[2]))
+ return 1;
+
+ if (strncasecmp (t, "sr", 2) == 0 && is_regname_end (t[2]))
+ return 2;
+
+ if (*t == '0' && is_regname_end (t[1]))
+ return 0;
+
+ val = strtol (t, & endt, 0);
+
+ if (val < 1 || val > 15)
+ return -1;
+
+ if (is_regname_end (*endt))
+ return val;
+
+ return -1;
+}
+
+static int
+msp430_srcoperand (struct msp430_operand_s * op,
+ char * l,
+ int bin,
+ bfd_boolean * imm_op,
+ bfd_boolean allow_20bit_values,
+ bfd_boolean constants_allowed)
+{
+ char * end;
+ char *__tl = l;
+
+ /* Check if an immediate #VALUE. The hash sign should be only at the beginning! */
+ if (*l == '#')
+ {
+ char *h = l;
+ int vshift = -1;
+ int rval = 0;
+
+ /* Check if there is:
+ llo(x) - least significant 16 bits, x &= 0xffff
+ lhi(x) - x = (x >> 16) & 0xffff,
+ hlo(x) - x = (x >> 32) & 0xffff,
+ hhi(x) - x = (x >> 48) & 0xffff
+ The value _MUST_ be constant expression: #hlo(1231231231). */
+
+ *imm_op = TRUE;
+
+ if (strncasecmp (h, "#llo(", 5) == 0)
+ {
+ vshift = 0;
+ rval = 3;
+ }
+ else if (strncasecmp (h, "#lhi(", 5) == 0)
+ {
+ vshift = 1;
+ rval = 3;
+ }
+ else if (strncasecmp (h, "#hlo(", 5) == 0)
+ {
+ vshift = 2;
+ rval = 3;
+ }
+ else if (strncasecmp (h, "#hhi(", 5) == 0)
+ {
+ vshift = 3;
+ rval = 3;
+ }
+ else if (strncasecmp (h, "#lo(", 4) == 0)
+ {
+ vshift = 0;
+ rval = 2;
+ }
+ else if (strncasecmp (h, "#hi(", 4) == 0)
+ {
+ vshift = 1;
+ rval = 2;
+ }
+
+ op->reg = 0; /* Reg PC. */
+ op->am = 3;
+ op->ol = 1; /* Immediate will follow an instruction. */
+ __tl = h + 1 + rval;
+ op->mode = OP_EXP;
+ op->vshift = vshift;
+
+ end = parse_exp (__tl, &(op->exp));
+ if (end != NULL && *end != 0 && *end != ')' )
+ {
+ as_bad (_("extra characters '%s' at end of immediate expression '%s'"), end, l);
+ return 1;
+ }
+ if (op->exp.X_op == O_constant)
+ {
+ int x = op->exp.X_add_number;
+
+ if (vshift == 0)
+ {
+ x = x & 0xffff;
+ op->exp.X_add_number = x;
+ }
+ else if (vshift == 1)
+ {
+ x = (x >> 16) & 0xffff;
+ op->exp.X_add_number = x;
+ op->vshift = 0;
+ }
+ else if (vshift > 1)
+ {
+ if (x < 0)
+ op->exp.X_add_number = -1;
+ else
+ op->exp.X_add_number = 0; /* Nothing left. */
+ x = op->exp.X_add_number;
+ op->vshift = 0;
+ }
+
+ if (allow_20bit_values)
+ {
+ if (op->exp.X_add_number > 0xfffff || op->exp.X_add_number < -524288)
+ {
+ as_bad (_("value 0x%x out of extended range."), x);
+ return 1;
+ }
+ }
+ else if (op->exp.X_add_number > 65535 || op->exp.X_add_number < -32768)
+ {
+ as_bad (_("value %d out of range. Use #lo() or #hi()"), x);
+ return 1;
+ }
+
+ /* Now check constants. */
+ /* Substitute register mode with a constant generator if applicable. */
+
+ if (!allow_20bit_values)
+ x = (short) x; /* Extend sign. */
+
+ if (! constants_allowed)
+ ;
+ else if (x == 0)
+ {
+ op->reg = 3;
+ op->am = 0;
+ op->ol = 0;
+ op->mode = OP_REG;
+ }
+ else if (x == 1)
+ {
+ op->reg = 3;
+ op->am = 1;
+ op->ol = 0;
+ op->mode = OP_REG;
+ }
+ else if (x == 2)
+ {
+ op->reg = 3;
+ op->am = 2;
+ op->ol = 0;
+ op->mode = OP_REG;
+ }
+ else if (x == -1)
+ {
+ op->reg = 3;
+ op->am = 3;
+ op->ol = 0;
+ op->mode = OP_REG;
+ }
+ else if (x == 4)
+ {
+ if (bin == 0x1200 && ! target_is_430x ())
+ {
+ /* CPU4: The shorter form of PUSH #4 is not supported on MSP430. */
+ if (silicon_errata_warn & SILICON_ERRATA_CPU4)
+ as_warn (_("cpu4: not converting PUSH #4 to shorter form"));
+ /* No need to check silicon_errata_fixes - this fix is always implemented. */
+ }
+ else
+ {
+ op->reg = 2;
+ op->am = 2;
+ op->ol = 0;
+ op->mode = OP_REG;
+ }
+ }
+ else if (x == 8)
+ {
+ if (bin == 0x1200 && ! target_is_430x ())
+ {
+ /* CPU4: The shorter form of PUSH #8 is not supported on MSP430. */
+ if (silicon_errata_warn & SILICON_ERRATA_CPU4)
+ as_warn (_("cpu4: not converting PUSH #8 to shorter form"));
+ }
+ else
+ {
+ op->reg = 2;
+ op->am = 3;
+ op->ol = 0;
+ op->mode = OP_REG;
+ }
+ }
+ }
+ else if (op->exp.X_op == O_symbol)
+ {
+ if (vshift > 1)
+ as_bad (_("error: unsupported #foo() directive used on symbol"));
+ op->mode = OP_EXP;
+ }
+ else if (op->exp.X_op == O_big)
+ {
+ short x;
+
+ if (vshift != -1)
+ {
+ op->exp.X_op = O_constant;
+ op->exp.X_add_number = 0xffff & generic_bignum[vshift];
+ x = op->exp.X_add_number;
+ op->vshift = 0;
+ }
+ else
+ {
+ as_bad (_
+ ("unknown expression in operand %s. Use #llo(), #lhi(), #hlo() or #hhi()"),
+ l);
+ return 1;
+ }
+
+ if (x == 0)
+ {
+ op->reg = 3;
+ op->am = 0;
+ op->ol = 0;
+ op->mode = OP_REG;
+ }
+ else if (x == 1)
+ {
+ op->reg = 3;
+ op->am = 1;
+ op->ol = 0;
+ op->mode = OP_REG;
+ }
+ else if (x == 2)
+ {
+ op->reg = 3;
+ op->am = 2;
+ op->ol = 0;
+ op->mode = OP_REG;
+ }
+ else if (x == -1)
+ {
+ op->reg = 3;
+ op->am = 3;
+ op->ol = 0;
+ op->mode = OP_REG;
+ }
+ else if (x == 4)
+ {
+ op->reg = 2;
+ op->am = 2;
+ op->ol = 0;
+ op->mode = OP_REG;
+ }
+ else if (x == 8)
+ {
+ op->reg = 2;
+ op->am = 3;
+ op->ol = 0;
+ op->mode = OP_REG;
+ }
+ }
+ /* Redundant (yet) check. */
+ else if (op->exp.X_op == O_register)
+ as_bad
+ (_("Registers cannot be used within immediate expression [%s]"), l);
+ else
+ as_bad (_("unknown operand %s"), l);
+
+ return 0;
+ }
+
+ /* Check if absolute &VALUE (assume that we can construct something like ((a&b)<<7 + 25). */
+ if (*l == '&')
+ {
+ char *h = l;
+
+ op->reg = 2; /* Reg 2 in absolute addr mode. */
+ op->am = 1; /* Mode As == 01 bin. */
+ op->ol = 1; /* Immediate value followed by instruction. */
+ __tl = h + 1;
+ end = parse_exp (__tl, &(op->exp));
+ if (end != NULL && *end != 0)
+ {
+ as_bad (_("extra characters '%s' at the end of absolute operand '%s'"), end, l);
+ return 1;
+ }
+ op->mode = OP_EXP;
+ op->vshift = 0;
+ if (op->exp.X_op == O_constant)
+ {
+ int x = op->exp.X_add_number;
+
+ if (allow_20bit_values)
+ {
+ if (x > 0xfffff || x < -(0x7ffff))
+ {
+ as_bad (_("value 0x%x out of extended range."), x);
+ return 1;
+ }
+ }
+ else if (x > 65535 || x < -32768)
+ {
+ as_bad (_("value out of range: 0x%x"), x);
+ return 1;
+ }
+ }
+ else if (op->exp.X_op == O_symbol)
+ ;
+ else
+ {
+ /* Redundant (yet) check. */
+ if (op->exp.X_op == O_register)
+ as_bad
+ (_("Registers cannot be used within absolute expression [%s]"), l);
+ else
+ as_bad (_("unknown expression in operand %s"), l);
+ return 1;
+ }
+ return 0;
+ }
+
+ /* Check if indirect register mode @Rn / postincrement @Rn+. */
+ if (*l == '@')
+ {
+ char *t = l;
+ char *m = strchr (l, '+');
+
+ if (t != l)
+ {
+ as_bad (_("unknown addressing mode %s"), l);
+ return 1;
+ }
+
+ t++;
+
+ if ((op->reg = check_reg (t)) == -1)
+ {
+ as_bad (_("Bad register name %s"), t);
+ return 1;
+ }
+
+ op->mode = OP_REG;
+ op->am = m ? 3 : 2;
+ op->ol = 0;
+
+ /* PC cannot be used in indirect addressing. */
+ if (target_is_430xv2 () && op->reg == 0)
+ {
+ as_bad (_("cannot use indirect addressing with the PC"));
+ return 1;
+ }
+
+ return 0;
+ }
+
+ /* Check if register indexed X(Rn). */
+ do
+ {
+ char *h = strrchr (l, '(');
+ char *m = strrchr (l, ')');
+ char *t;
+
+ *imm_op = TRUE;
+
+ if (!h)
+ break;
+ if (!m)
+ {
+ as_bad (_("')' required"));
+ return 1;
+ }
+
+ t = h;
+ op->am = 1;
+ op->ol = 1;
+
+ /* Extract a register. */
+ if ((op->reg = check_reg (t + 1)) == -1)
+ {
+ as_bad (_
+ ("unknown operator %s. Did you mean X(Rn) or #[hl][hl][oi](CONST) ?"),
+ l);
+ return 1;
+ }
+
+ if (op->reg == 2)
+ {
+ as_bad (_("r2 should not be used in indexed addressing mode"));
+ return 1;
+ }
+
+ /* Extract constant. */
+ __tl = l;
+ *h = 0;
+ op->mode = OP_EXP;
+ op->vshift = 0;
+ end = parse_exp (__tl, &(op->exp));
+ if (end != NULL && *end != 0)
+ {
+ as_bad (_("extra characters '%s' at end of operand '%s'"), end, l);
+ return 1;
+ }
+ if (op->exp.X_op == O_constant)
+ {
+ int x = op->exp.X_add_number;
+
+ if (allow_20bit_values)
+ {
+ if (x > 0xfffff || x < - (0x7ffff))
+ {
+ as_bad (_("value 0x%x out of extended range."), x);
+ return 1;
+ }
+ }
+ else if (x > 65535 || x < -32768)
+ {
+ as_bad (_("value out of range: 0x%x"), x);
+ return 1;
+ }
+
+ if (x == 0)
+ {
+ op->mode = OP_REG;
+ op->am = 2;
+ op->ol = 0;
+ return 0;
+ }
+
+ if (op->reg == 1 && (x & 1))
+ {
+ if (silicon_errata_fix & SILICON_ERRATA_CPU8)
+ as_bad (_("CPU8: Stack pointer accessed with an odd offset"));
+ else if (silicon_errata_warn & SILICON_ERRATA_CPU8)
+ as_warn (_("CPU8: Stack pointer accessed with an odd offset"));
+ }
+ }
+ else if (op->exp.X_op == O_symbol)
+ ;
+ else
+ {
+ /* Redundant (yet) check. */
+ if (op->exp.X_op == O_register)
+ as_bad
+ (_("Registers cannot be used as a prefix of indexed expression [%s]"), l);
+ else
+ as_bad (_("unknown expression in operand %s"), l);
+ return 1;
+ }
+
+ return 0;
+ }
+ while (0);
+
+ /* Possibly register mode 'mov r1,r2'. */
+ if ((op->reg = check_reg (l)) != -1)
+ {
+ op->mode = OP_REG;
+ op->am = 0;
+ op->ol = 0;
+ return 0;
+ }
+
+ /* Symbolic mode 'mov a, b' == 'mov x(pc), y(pc)'. */
+ op->mode = OP_EXP;
+ op->reg = 0; /* PC relative... be careful. */
+ /* An expression starting with a minus sign is a constant, not an address. */
+ op->am = (*l == '-' ? 3 : 1);
+ op->ol = 1;
+ op->vshift = 0;
+ __tl = l;
+ end = parse_exp (__tl, &(op->exp));
+ if (end != NULL && * end != 0)
+ {
+ as_bad (_("extra characters '%s' at end of operand '%s'"), end, l);
+ return 1;
+ }
+ return 0;
+}
+
+
+static int
+msp430_dstoperand (struct msp430_operand_s * op,
+ char * l,
+ int bin,
+ bfd_boolean allow_20bit_values,
+ bfd_boolean constants_allowed)
+{
+ int dummy;
+ int ret = msp430_srcoperand (op, l, bin, & dummy,
+ allow_20bit_values,
+ constants_allowed);
+
+ if (ret)
+ return ret;
+
+ if (op->am == 2)
+ {
+ char *__tl = (char *) "0";
+
+ op->mode = OP_EXP;
+ op->am = 1;
+ op->ol = 1;
+ op->vshift = 0;
+ (void) parse_exp (__tl, &(op->exp));
+
+ if (op->exp.X_op != O_constant || op->exp.X_add_number != 0)
+ {
+ as_bad (_("Internal bug. Try to use 0(r%d) instead of @r%d"),
+ op->reg, op->reg);
+ return 1;
+ }
+ return 0;
+ }
+
+ if (op->am > 1)
+ {
+ as_bad (_
+ ("this addressing mode is not applicable for destination operand"));
+ return 1;
+ }
+ return 0;
+}
+
+/* Attempt to encode a MOVA instruction with the given operands.
+ Returns the length of the encoded instruction if successful
+ or 0 upon failure. If the encoding fails, an error message
+ will be returned if a pointer is provided. */
+
+static int
+try_encode_mova (bfd_boolean imm_op,
+ int bin,
+ struct msp430_operand_s * op1,
+ struct msp430_operand_s * op2,
+ const char ** error_message_return)
+{
+ short ZEROS = 0;
+ char *frag;
+ int where;
+
+ /* Only a restricted subset of the normal MSP430 addressing modes
+ are supported here, so check for the ones that are allowed. */
+ if (imm_op)
+ {
+ if (op1->mode == OP_EXP)
+ {
+ if (op2->mode != OP_REG)
+ {
+ if (error_message_return != NULL)
+ * error_message_return = _("expected register as second argument of %s");
+ return 0;
+ }
+
+ if (op1->am == 3)
+ {
+ /* MOVA #imm20, Rdst. */
+ bin |= 0x80 | op2->reg;
+ frag = frag_more (4);
+ where = frag - frag_now->fr_literal;
+ if (op1->exp.X_op == O_constant)
+ {
+ bin |= ((op1->exp.X_add_number >> 16) & 0xf) << 8;
+ bfd_putl16 ((bfd_vma) bin, frag);
+ bfd_putl16 (op1->exp.X_add_number & 0xffff, frag + 2);
+ }
+ else
+ {
+ bfd_putl16 ((bfd_vma) bin, frag);
+ fix_new_exp (frag_now, where, 4, &(op1->exp), FALSE,
+ BFD_RELOC_MSP430X_ABS20_ADR_SRC);
+ bfd_putl16 ((bfd_vma) ZEROS, frag + 2);
+ }
+
+ return 4;
+ }
+ else if (op1->am == 1)
+ {
+ /* MOVA z16(Rsrc), Rdst. */
+ bin |= 0x30 | (op1->reg << 8) | op2->reg;
+ frag = frag_more (4);
+ where = frag - frag_now->fr_literal;
+ bfd_putl16 ((bfd_vma) bin, frag);
+ if (op1->exp.X_op == O_constant)
+ {
+ if (op1->exp.X_add_number > 0xffff
+ || op1->exp.X_add_number < -(0x7fff))
+ {
+ if (error_message_return != NULL)
+ * error_message_return = _("index value too big for %s");
+ return 0;
+ }
+ bfd_putl16 (op1->exp.X_add_number & 0xffff, frag + 2);
+ }
+ else
+ {
+ bfd_putl16 ((bfd_vma) ZEROS, frag + 2);
+ fix_new_exp (frag_now, where + 2, 2, &(op1->exp), FALSE,
+ op1->reg == 0 ?
+ BFD_RELOC_MSP430X_PCR16 :
+ BFD_RELOC_MSP430X_ABS16);
+ }
+ return 4;
+ }
+
+ if (error_message_return != NULL)
+ * error_message_return = _("unexpected addressing mode for %s");
+ return 0;
+ }
+ else if (op1->am == 0)
+ {
+ /* MOVA Rsrc, ... */
+ if (op2->mode == OP_REG)
+ {
+ bin |= 0xc0 | (op1->reg << 8) | op2->reg;
+ frag = frag_more (2);
+ where = frag - frag_now->fr_literal;
+ bfd_putl16 ((bfd_vma) bin, frag);
+ return 2;
+ }
+ else if (op2->am == 1)
+ {
+ if (op2->reg == 2)
+ {
+ /* MOVA Rsrc, &abs20. */
+ bin |= 0x60 | (op1->reg << 8);
+ frag = frag_more (4);
+ where = frag - frag_now->fr_literal;
+ if (op2->exp.X_op == O_constant)
+ {
+ bin |= (op2->exp.X_add_number >> 16) & 0xf;
+ bfd_putl16 ((bfd_vma) bin, frag);
+ bfd_putl16 (op2->exp.X_add_number & 0xffff, frag + 2);
+ }
+ else
+ {
+ bfd_putl16 ((bfd_vma) bin, frag);
+ bfd_putl16 ((bfd_vma) ZEROS, frag + 2);
+ fix_new_exp (frag_now, where, 4, &(op2->exp), FALSE,
+ BFD_RELOC_MSP430X_ABS20_ADR_DST);
+ }
+ return 4;
+ }
+
+ /* MOVA Rsrc, z16(Rdst). */
+ bin |= 0x70 | (op1->reg << 8) | op2->reg;
+ frag = frag_more (4);
+ where = frag - frag_now->fr_literal;
+ bfd_putl16 ((bfd_vma) bin, frag);
+ if (op2->exp.X_op == O_constant)
+ {
+ if (op2->exp.X_add_number > 0xffff
+ || op2->exp.X_add_number < -(0x7fff))
+ {
+ if (error_message_return != NULL)
+ * error_message_return = _("index value too big for %s");
+ return 0;
+ }
+ bfd_putl16 (op2->exp.X_add_number & 0xffff, frag + 2);
+ }
+ else
+ {
+ bfd_putl16 ((bfd_vma) ZEROS, frag + 2);
+ fix_new_exp (frag_now, where + 2, 2, &(op2->exp), FALSE,
+ op2->reg == 0 ?
+ BFD_RELOC_MSP430X_PCR16 :
+ BFD_RELOC_MSP430X_ABS16);
+ }
+ return 4;
+ }
+
+ if (error_message_return != NULL)
+ * error_message_return = _("unexpected addressing mode for %s");
+ return 0;
+ }
+ }
+
+ /* imm_op == FALSE. */
+
+ if (op1->reg == 2 && op1->am == 1 && op1->mode == OP_EXP)
+ {
+ /* MOVA &abs20, Rdst. */
+ if (op2->mode != OP_REG)
+ {
+ if (error_message_return != NULL)
+ * error_message_return = _("expected register as second argument of %s");
+ return 0;
+ }
+
+ if (op2->reg == 2 || op2->reg == 3)
+ {
+ if (error_message_return != NULL)
+ * error_message_return = _("constant generator destination register found in %s");
+ return 0;
+ }
+
+ bin |= 0x20 | op2->reg;
+ frag = frag_more (4);
+ where = frag - frag_now->fr_literal;
+ if (op1->exp.X_op == O_constant)
+ {
+ bin |= ((op1->exp.X_add_number >> 16) & 0xf) << 8;
+ bfd_putl16 ((bfd_vma) bin, frag);
+ bfd_putl16 (op1->exp.X_add_number & 0xffff, frag + 2);
+ }
+ else
+ {
+ bfd_putl16 ((bfd_vma) bin, frag);
+ bfd_putl16 ((bfd_vma) ZEROS, frag + 2);
+ fix_new_exp (frag_now, where, 4, &(op1->exp), FALSE,
+ BFD_RELOC_MSP430X_ABS20_ADR_SRC);
+ }
+ return 4;
+ }
+ else if (op1->mode == OP_REG)
+ {
+ if (op1->am == 3)
+ {
+ /* MOVA @Rsrc+, Rdst. */
+ if (op2->mode != OP_REG)
+ {
+ if (error_message_return != NULL)
+ * error_message_return = _("expected register as second argument of %s");
+ return 0;
+ }
+
+ if (op2->reg == 2 || op2->reg == 3)
+ {
+ if (error_message_return != NULL)
+ * error_message_return = _("constant generator destination register found in %s");
+ return 0;
+ }
+
+ if (op1->reg == 2 || op1->reg == 3)
+ {
+ if (error_message_return != NULL)
+ * error_message_return = _("constant generator source register found in %s");
+ return 0;
+ }
+
+ bin |= 0x10 | (op1->reg << 8) | op2->reg;
+ frag = frag_more (2);
+ where = frag - frag_now->fr_literal;
+ bfd_putl16 ((bfd_vma) bin, frag);
+ return 2;
+ }
+ else if (op1->am == 2)
+ {
+ /* MOVA @Rsrc,Rdst */
+ if (op2->mode != OP_REG)
+ {
+ if (error_message_return != NULL)
+ * error_message_return = _("expected register as second argument of %s");
+ return 0;
+ }
+
+ if (op2->reg == 2 || op2->reg == 3)
+ {
+ if (error_message_return != NULL)
+ * error_message_return = _("constant generator destination register found in %s");
+ return 0;
+ }
+
+ if (op1->reg == 2 || op1->reg == 3)
+ {
+ if (error_message_return != NULL)
+ * error_message_return = _("constant generator source register found in %s");
+ return 0;
+ }
+
+ bin |= (op1->reg << 8) | op2->reg;
+ frag = frag_more (2);
+ where = frag - frag_now->fr_literal;
+ bfd_putl16 ((bfd_vma) bin, frag);
+ return 2;
+ }
+ }
+
+ if (error_message_return != NULL)
+ * error_message_return = _("unexpected addressing mode for %s");
+
+ return 0;
+}
+
+#define NOP_CHECK_INTERRUPT (1 << 0)
+#define NOP_CHECK_CPU12 (1 << 1)
+#define NOP_CHECK_CPU19 (1 << 2)
+
+static signed int check_for_nop = 0;
+
+#define is_opcode(NAME) (strcmp (opcode->name, NAME) == 0)
+
+/* is_{e,d}int only check the explicit enabling/disabling of interrupts.
+ For MOV insns, more sophisticated processing is needed to determine if they
+ result in enabling/disabling interrupts. */
+#define is_dint(OPCODE, BIN) ((strcmp (OPCODE, "dint") == 0) \
+ || ((strcmp (OPCODE, "bic") == 0) \
+ && BIN == 0xc232) \
+ || ((strcmp (OPCODE, "clr") == 0) \
+ && BIN == 0x4302))
+
+#define is_eint(OPCODE, BIN) ((strcmp (OPCODE, "eint") == 0) \
+ || ((strcmp (OPCODE, "bis") == 0) \
+ && BIN == 0xd232))
+
+const char * const INSERT_NOP_BEFORE_EINT = "NOP inserted here, before an interrupt enable instruction";
+const char * const INSERT_NOP_AFTER_DINT = "NOP inserted here, after an interrupt disable instruction";
+const char * const INSERT_NOP_AFTER_EINT = "NOP inserted here, after an interrupt enable instruction";
+const char * const INSERT_NOP_BEFORE_UNKNOWN = "NOP inserted here, before this interrupt state change";
+const char * const INSERT_NOP_AFTER_UNKNOWN ="NOP inserted here, after the instruction that changed interrupt state";
+const char * const INSERT_NOP_AT_EOF = "NOP inserted after the interrupt state change at the end of the file";
+
+const char * const WARN_NOP_BEFORE_EINT = "a NOP might be needed here, before an interrupt enable instruction";
+const char * const WARN_NOP_AFTER_DINT = "a NOP might be needed here, after an interrupt disable instruction";
+const char * const WARN_NOP_AFTER_EINT = "a NOP might be needed here, after an interrupt enable instruction";
+const char * const WARN_NOP_BEFORE_UNKNOWN = "a NOP might be needed here, before this interrupt state change";
+const char * const WARN_NOP_AFTER_UNKNOWN = "a NOP might also be needed here, after the instruction that changed interrupt state";
+const char * const WARN_NOP_AT_EOF = "a NOP might be needed after the interrupt state change at the end of the file";
+
+static void
+gen_nop (void)
+{
+ char *frag;
+ frag = frag_more (2);
+ bfd_putl16 ((bfd_vma) 0x4303 /* NOP */, frag);
+ dwarf2_emit_insn (2);
+}
+
+/* Insert/inform about adding a NOP if this insn enables interrupts. */
+
+static void
+warn_eint_nop (bfd_boolean prev_insn_is_nop, bfd_boolean prev_insn_is_dint)
+{
+ if (prev_insn_is_nop
+ /* If the last insn was a DINT, we will have already warned that a NOP is
+ required after it. */
+ || prev_insn_is_dint
+ /* 430 ISA does not require a NOP before EINT. */
+ || (! target_is_430x ()))
+ return;
+
+ if (gen_interrupt_nops)
+ {
+ gen_nop ();
+ if (warn_interrupt_nops)
+ as_warn (_(INSERT_NOP_BEFORE_EINT));
+ }
+ else if (warn_interrupt_nops)
+ as_warn (_(WARN_NOP_BEFORE_EINT));
+}
+
+/* Use when unsure what effect the insn will have on the interrupt status,
+ to insert/warn about adding a NOP before the current insn. */
+
+static void
+warn_unsure_interrupt (bfd_boolean prev_insn_is_nop,
+ bfd_boolean prev_insn_is_dint)
+{
+ if (prev_insn_is_nop
+ /* If the last insn was a DINT, we will have already warned that a NOP is
+ required after it. */
+ || prev_insn_is_dint
+ /* 430 ISA does not require a NOP before EINT or DINT. */
+ || (! target_is_430x ()))
+ return;
+
+ if (gen_interrupt_nops)
+ {
+ gen_nop ();
+ if (warn_interrupt_nops)
+ as_warn (_(INSERT_NOP_BEFORE_UNKNOWN));
+ }
+ else if (warn_interrupt_nops)
+ as_warn (_(WARN_NOP_BEFORE_UNKNOWN));
+}
+
+/* Parse instruction operands.
+ Return binary opcode. */
+
+static unsigned int
+msp430_operands (struct msp430_opcode_s * opcode, char * line)
+{
+ int bin = opcode->bin_opcode; /* Opcode mask. */
+ int insn_length = 0;
+ char l1[MAX_OP_LEN], l2[MAX_OP_LEN];
+ char *frag;
+ char *end;
+ int where;
+ struct msp430_operand_s op1, op2;
+ int res = 0;
+ static short ZEROS = 0;
+ bfd_boolean byte_op, imm_op;
+ int op_length = 0;
+ int fmt;
+ int extended = 0x1800;
+ bfd_boolean extended_op = FALSE;
+ bfd_boolean addr_op;
+ const char * error_message;
+ static signed int repeat_count = 0;
+ static bfd_boolean prev_insn_is_nop = FALSE;
+ static bfd_boolean prev_insn_is_dint = FALSE;
+ static bfd_boolean prev_insn_is_eint = FALSE;
+ /* We might decide before the end of the function that the current insn is
+ equivalent to DINT/EINT. */
+ bfd_boolean this_insn_is_dint = FALSE;
+ bfd_boolean this_insn_is_eint = FALSE;
+ bfd_boolean fix_emitted;
+
+ /* Opcode is the one from opcodes table
+ line contains something like
+ [.w] @r2+, 5(R1)
+ or
+ .b @r2+, 5(R1). */
+
+ byte_op = FALSE;
+ addr_op = FALSE;
+ if (*line == '.')
+ {
+ bfd_boolean check = FALSE;
+ ++ line;
+
+ switch (TOLOWER (* line))
+ {
+ case 'b':
+ /* Byte operation. */
+ bin |= BYTE_OPERATION;
+ byte_op = TRUE;
+ check = TRUE;
+ break;
+
+ case 'a':
+ /* "Address" ops work on 20-bit values. */
+ addr_op = TRUE;
+ bin |= BYTE_OPERATION;
+ check = TRUE;
+ break;
+
+ case 'w':
+ /* Word operation - this is the default. */
+ check = TRUE;
+ break;
+
+ case 0:
+ case ' ':
+ case '\n':
+ case '\r':
+ as_warn (_("no size modifier after period, .w assumed"));
+ break;
+
+ default:
+ as_bad (_("unrecognised instruction size modifier .%c"),
+ * line);
+ return 0;
+ }
+
+ if (check)
+ {
+ ++ line;
+
+ }
+ }
+
+ if (*line && ! ISSPACE (*line))
+ {
+ as_bad (_("junk found after instruction: %s.%s"),
+ opcode->name, line);
+ return 0;
+ }
+
+ /* Catch the case where the programmer has used a ".a" size modifier on an
+ instruction that does not support it. Look for an alternative extended
+ instruction that has the same name without the period. Eg: "add.a"
+ becomes "adda". Although this not an officially supported way of
+ specifying instruction aliases other MSP430 assemblers allow it. So we
+ support it for compatibility purposes. */
+ if (addr_op && opcode->fmt >= 0)
+ {
+ const char * old_name = opcode->name;
+ char real_name[32];
+
+ sprintf (real_name, "%sa", old_name);
+ opcode = hash_find (msp430_hash, real_name);
+ if (opcode == NULL)
+ {
+ as_bad (_("instruction %s.a does not exist"), old_name);
+ return 0;
+ }
+#if 0 /* Enable for debugging. */
+ as_warn ("treating %s.a as %s", old_name, real_name);
+#endif
+ addr_op = FALSE;
+ bin = opcode->bin_opcode;
+ }
+
+ if (opcode->fmt != -1
+ && opcode->insn_opnumb
+ && (!*line || *line == '\n'))
+ {
+ as_bad (ngettext ("instruction %s requires %d operand",
+ "instruction %s requires %d operands",
+ opcode->insn_opnumb),
+ opcode->name, opcode->insn_opnumb);
+ return 0;
+ }
+
+ memset (l1, 0, sizeof (l1));
+ memset (l2, 0, sizeof (l2));
+ memset (&op1, 0, sizeof (op1));
+ memset (&op2, 0, sizeof (op2));
+
+ imm_op = FALSE;
+
+ if ((fmt = opcode->fmt) < 0)
+ {
+ if (! target_is_430x ())
+ {
+ as_bad (_("instruction %s requires MSP430X mcu"),
+ opcode->name);
+ return 0;
+ }
+
+ fmt = (-fmt) - 1;
+ extended_op = TRUE;
+ }
+
+ if (repeat_count)
+ {
+ /* If requested set the extended instruction repeat count. */
+ if (extended_op)
+ {
+ if (repeat_count > 0)
+ extended |= (repeat_count - 1);
+ else
+ extended |= (1 << 7) | (- repeat_count);
+ }
+ else
+ as_bad (_("unable to repeat %s insn"), opcode->name);
+
+ repeat_count = 0;
+ }
+
+ /* The previous instruction set this flag if it wants to check if this insn
+ is a NOP. */
+ if (check_for_nop)
+ {
+ if (! is_opcode ("nop"))
+ {
+ do
+ {
+ switch (check_for_nop & - check_for_nop)
+ {
+ case NOP_CHECK_INTERRUPT:
+ /* NOP_CHECK_INTERRUPT rules:
+ 1. 430 and 430x ISA require a NOP after DINT.
+ 2. Only the 430x ISA requires NOP before EINT (this has
+ been dealt with in the previous call to this function).
+ 3. Only the 430x ISA requires NOP after every EINT.
+ CPU42 errata. */
+ if (gen_interrupt_nops || warn_interrupt_nops)
+ {
+ if (prev_insn_is_dint)
+ {
+ if (gen_interrupt_nops)
+ {
+ gen_nop ();
+ if (warn_interrupt_nops)
+ as_warn (_(INSERT_NOP_AFTER_DINT));
+ }
+ else
+ as_warn (_(WARN_NOP_AFTER_DINT));
+ }
+ else if (prev_insn_is_eint)
+ {
+ if (gen_interrupt_nops)
+ {
+ gen_nop ();
+ if (warn_interrupt_nops)
+ as_warn (_(INSERT_NOP_AFTER_EINT));
+ }
+ else
+ as_warn (_(WARN_NOP_AFTER_EINT));
+ }
+ /* If we get here it's because the last instruction was
+ determined to either disable or enable interrupts, but
+ we're not sure which.
+ We have no information yet about what effect the
+ current instruction has on interrupts, that has to be
+ sorted out later.
+ The last insn may have required a NOP after it, so we
+ deal with that now. */
+ else
+ {
+ if (gen_interrupt_nops)
+ {
+ gen_nop ();
+ if (warn_interrupt_nops)
+ as_warn (_(INSERT_NOP_AFTER_UNKNOWN));
+ }
+ else
+ /* warn_unsure_interrupt was called on the previous
+ insn. */
+ as_warn (_(WARN_NOP_AFTER_UNKNOWN));
+ }
+ }
+ break;
+
+ case NOP_CHECK_CPU12:
+ if (silicon_errata_warn & SILICON_ERRATA_CPU12)
+ as_warn (_("CPU12: CMP/BIT with PC destination ignores next instruction"));
+
+ if (silicon_errata_fix & SILICON_ERRATA_CPU12)
+ gen_nop ();
+ break;
+
+ case NOP_CHECK_CPU19:
+ if (silicon_errata_warn & SILICON_ERRATA_CPU19)
+ as_warn (_("CPU19: Instruction setting CPUOFF must be followed by a NOP"));
+
+ if (silicon_errata_fix & SILICON_ERRATA_CPU19)
+ gen_nop ();
+ break;
+
+ default:
+ as_bad (_("internal error: unknown nop check state"));
+ break;
+ }
+ check_for_nop &= ~ (check_for_nop & - check_for_nop);
+ }
+ while (check_for_nop);
+ }
+ check_for_nop = 0;
+ }
+
+ switch (fmt)
+ {
+ case 0:
+ /* Emulated. */
+ switch (opcode->insn_opnumb)
+ {
+ case 0:
+ if (is_opcode ("eint"))
+ warn_eint_nop (prev_insn_is_nop, prev_insn_is_dint);
+
+ /* Set/clear bits instructions. */
+ if (extended_op)
+ {
+ if (!addr_op)
+ extended |= BYTE_OPERATION;
+
+ /* Emit the extension word. */
+ insn_length += 2;
+ frag = frag_more (2);
+ bfd_putl16 (extended, frag);
+ }
+
+ insn_length += 2;
+ frag = frag_more (2);
+ bfd_putl16 ((bfd_vma) bin, frag);
+ dwarf2_emit_insn (insn_length);
+ break;
+
+ case 1:
+ /* Something which works with destination operand. */
+ line = extract_operand (line, l1, sizeof (l1));
+ res = msp430_dstoperand (&op1, l1, opcode->bin_opcode, extended_op, TRUE);
+ if (res)
+ break;
projects / deliverable / binutils-gdb.git / blobdiff