projects
/
deliverable
/
binutils-gdb.git
/ blobdiff
commit
grep
author
committer
pickaxe
?
search:
re
summary
|
shortlog
|
log
|
commit
|
commitdiff
|
tree
raw
|
inline
| side by side
x86: further refine SSE check (SSE4a, SHA, GFNI)
[deliverable/binutils-gdb.git]
/
gas
/
doc
/
c-m32r.texi
diff --git
a/gas/doc/c-m32r.texi
b/gas/doc/c-m32r.texi
index 52a73c38700da60e68316aca38bece1eb2f55bf2..afce4498ff5f2d028cb30df9372e9152ae95a83c 100644
(file)
--- a/
gas/doc/c-m32r.texi
+++ b/
gas/doc/c-m32r.texi
@@
-1,6
+1,4
@@
-@c Copyright 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 2000,
-@c 2003, 2004
-@c Free Software Foundation, Inc.
+@c Copyright (C) 1991-2019 Free Software Foundation, Inc.
@c This is part of the GAS manual.
@c For copying conditions, see the file as.texinfo.
@ifset GENERIC
@c This is part of the GAS manual.
@c For copying conditions, see the file as.texinfo.
@ifset GENERIC
@@
-26,7
+24,7
@@
@cindex options, M32R
@cindex M32R options
@cindex options, M32R
@cindex M32R options
-The Rene
ase
M32R version of @code{@value{AS}} has a few machine
+The Rene
sas
M32R version of @code{@value{AS}} has a few machine
dependent options:
@table @code
dependent options:
@table @code
@@
-46,7
+44,7
@@
the original instructions.
@cindex @samp{-m32rx} option, M32R2
@cindex architecture options, M32R2
@cindex M32R architecture options
@cindex @samp{-m32rx} option, M32R2
@cindex architecture options, M32R2
@cindex M32R architecture options
-This option changes the target processor to the
the
M32R2
+This option changes the target processor to the M32R2
microprocessor.
@item -m32r
microprocessor.
@item -m32r
@@
-55,7
+53,7
@@
microprocessor.
@cindex M32R architecture options
This option can be used to restore the assembler's default behaviour of
assembling for the M32R microprocessor. This can be useful if the
@cindex M32R architecture options
This option can be used to restore the assembler's default behaviour of
assembling for the M32R microprocessor. This can be useful if the
-default has been changed by a previous command
line option.
+default has been changed by a previous command
-
line option.
@item -little
@cindex @code{-little} option, M32R
@item -little
@cindex @code{-little} option, M32R
@@
-65,7
+63,7
@@
configured.
@item -EL
@cindex @code{-EL} option, M32R
@item -EL
@cindex @code{-EL} option, M32R
-This is a synon
u
m for @emph{-little}.
+This is a synon
y
m for @emph{-little}.
@item -big
@cindex @code{-big} option, M32R
@item -big
@cindex @code{-big} option, M32R
@@
-74,7
+72,7
@@
data.
@item -EB
@cindex @code{-EB} option, M32R
@item -EB
@cindex @code{-EB} option, M32R
-This is a synon
u
m for @emph{-big}.
+This is a synon
y
m for @emph{-big}.
@item -KPIC
@cindex @code{-KPIC} option, M32R
@item -KPIC
@cindex @code{-KPIC} option, M32R
@@
-110,7
+108,7
@@
implies @emph{-parallel}.
Instructs @code{@value{AS}} to produce warning messages when
questionable parallel instructions are encountered. This option is
enabled by default, but @code{@value{GCC}} disables it when it invokes
Instructs @code{@value{AS}} to produce warning messages when
questionable parallel instructions are encountered. This option is
enabled by default, but @code{@value{GCC}} disables it when it invokes
-@code{@value{AS}} directly. Questionable instructions are those who
es
+@code{@value{AS}} directly. Questionable instructions are those who
se
behaviour would be different if they were executed sequentially. For
example the code fragment @samp{mv r1, r2 || mv r3, r1} produces a
different result from @samp{mv r1, r2 \n mv r3, r1} since the former
behaviour would be different if they were executed sequentially. For
example the code fragment @samp{mv r1, r2 || mv r3, r1} produces a
different result from @samp{mv r1, r2 \n mv r3, r1} since the former
@@
-135,7
+133,7
@@
option.
@item -ignore-parallel-conflicts
@cindex @samp{-ignore-parallel-conflicts} option, M32RX
This option tells the assembler's to stop checking parallel
@item -ignore-parallel-conflicts
@cindex @samp{-ignore-parallel-conflicts} option, M32RX
This option tells the assembler's to stop checking parallel
-instructions for contraint violations. This ability is provided for
+instructions for con
s
traint violations. This ability is provided for
hardware vendors testing chip designs and should not be used under
normal circumstances.
hardware vendors testing chip designs and should not be used under
normal circumstances.
@@
-157,8
+155,8
@@
option.
@item -warn-unmatched-high
@cindex @samp{-warn-unmatched-high} option, M32R
This option tells the assembler to produce a warning message if a
@item -warn-unmatched-high
@cindex @samp{-warn-unmatched-high} option, M32R
This option tells the assembler to produce a warning message if a
-@code{.high} pseudo op is encountered without a mat
hc
ing @code{.low}
-pseudo op. The presence of such an unmatche
s
pseudo op usually
+@code{.high} pseudo op is encountered without a mat
ch
ing @code{.low}
+pseudo op. The presence of such an unmatche
d
pseudo op usually
indicates a programming error.
@item -no-warn-unmatched-high
indicates a programming error.
@item -no-warn-unmatched-high
@@
-180,7
+178,7
@@
This is a shorter synonym for the @emph{-no-warn-unmatched-high} option.
@cindex directives, M32R
@cindex M32R directives
@cindex directives, M32R
@cindex M32R directives
-The Rene
ase
M32R version of @code{@value{AS}} has a few architecture
+The Rene
sas
M32R version of @code{@value{AS}} has a few architecture
specific directives:
@table @code
specific directives:
@table @code
@@
-192,7
+190,7
@@
places the lower 16-bits of the result into the immediate-field of the
instruction. For example:
@smallexample
instruction. For example:
@smallexample
- or3 r0, r0, #low(0x12345678) ; compute r0 = r0 | 0x5678
+ or3 r0, r0, #low(0x12345678) ; compute r0 = r0 | 0x5678
add3, r0, r0, #low(fred) ; compute r0 = r0 + low 16-bits of address of fred
@end smallexample
add3, r0, r0, #low(fred) ; compute r0 = r0 + low 16-bits of address of fred
@end smallexample
@@
-203,7
+201,7
@@
places the upper 16-bits of the result into the immediate-field of the
instruction. For example:
@smallexample
instruction. For example:
@smallexample
- seth r0, #high(0x12345678) ; compute r0 = 0x12340000
+ seth r0, #high(0x12345678) ; compute r0 = 0x12340000
seth, r0, #high(fred) ; compute r0 = upper 16-bits of address of fred
@end smallexample
seth, r0, #high(fred) ; compute r0 = upper 16-bits of address of fred
@end smallexample
@@
-211,7
+209,7
@@
instruction. For example:
@cindex @code{shigh} directive, M32R
The @code{shigh} directive is very similar to the @code{high}
directive. It also computes the value of its expression and places
@cindex @code{shigh} directive, M32R
The @code{shigh} directive is very similar to the @code{high}
directive. It also computes the value of its expression and places
-the upper 16-bits of the result into the immediate-field of the
+the upper 16-bits of the result into the immediate-field of the
instruction. The difference is that @code{shigh} also checks to see
if the lower 16-bits could be interpreted as a signed number, and if
so it assumes that a borrow will occur from the upper-16 bits. To
instruction. The difference is that @code{shigh} also checks to see
if the lower 16-bits could be interpreted as a signed number, and if
so it assumes that a borrow will occur from the upper-16 bits. To
@@
-237,15
+235,15
@@
treats its 16-bit immediate argument as unsigned whereas the
example:
@smallexample
example:
@smallexample
- seth r0, #shigh(0x00008000)
- add3 r0, r0, #low(0x00008000)
+ seth r0, #shigh(0x00008000)
+ add3 r0, r0, #low(0x00008000)
@end smallexample
Produces the correct result in r0, whereas:
@smallexample
@end smallexample
Produces the correct result in r0, whereas:
@smallexample
- seth r0, #shigh(0x00008000)
- or3 r0, r0, #low(0x00008000)
+ seth r0, #shigh(0x00008000)
+ or3 r0, r0, #low(0x00008000)
@end smallexample
Stores 0xffff8000 into r0.
@end smallexample
Stores 0xffff8000 into r0.
@@
-280,14
+278,14
@@
instructions in the M32R2 ISA as well as the ordinary M32R ISA.
The directive performs a similar thing as the @emph{-little} command
line option. It tells the assembler to start producing little-endian
code and data. This option should be used with care as producing
The directive performs a similar thing as the @emph{-little} command
line option. It tells the assembler to start producing little-endian
code and data. This option should be used with care as producing
-mixed-endian binary files is fr
o
ught with danger.
+mixed-endian binary files is fr
a
ught with danger.
@cindex @code{.big} directive, M32RX
@item .big
The directive performs a similar thing as the @emph{-big} command
line option. It tells the assembler to start producing big-endian
code and data. This option should be used with care as producing
@cindex @code{.big} directive, M32RX
@item .big
The directive performs a similar thing as the @emph{-big} command
line option. It tells the assembler to start producing big-endian
code and data. This option should be used with care as producing
-mixed-endian binary files is fr
o
ught with danger.
+mixed-endian binary files is fr
a
ught with danger.
@end table
@end table
@@
-323,17
+321,17
@@
neg instruction and the input to the move instruction.
@item instruction @samp{...} is for the M32RX only
This message is produced when the assembler encounters an instruction
which is only supported by the M32Rx processor, and the @samp{-m32rx}
@item instruction @samp{...} is for the M32RX only
This message is produced when the assembler encounters an instruction
which is only supported by the M32Rx processor, and the @samp{-m32rx}
-command
line flag has not been specified to allow assembly of such
-instructions.
+command
-
line flag has not been specified to allow assembly of such
+instructions.
@item unknown instruction @samp{...}
This message is produced when the assembler encounters an instruction
@item unknown instruction @samp{...}
This message is produced when the assembler encounters an instruction
-which it does not recogni
s
e.
+which it does not recogni
z
e.
@item only the NOP instruction can be issued in parallel on the m32r
This message is produced when the assembler encounters a parallel
instruction which does not involve a NOP instruction and the
@item only the NOP instruction can be issued in parallel on the m32r
This message is produced when the assembler encounters a parallel
instruction which does not involve a NOP instruction and the
-@samp{-m32rx} command
line flag has not been specified. Only the M32Rx
+@samp{-m32rx} command
-
line flag has not been specified. Only the M32Rx
processor is able to execute two instructions in parallel.
@item instruction @samp{...} cannot be executed in parallel.
processor is able to execute two instructions in parallel.
@item instruction @samp{...} cannot be executed in parallel.
@@
-343,7
+341,7
@@
executed in parallel.
@item Instructions share the same execution pipeline
This message is produced when the assembler encounters a parallel
@item Instructions share the same execution pipeline
This message is produced when the assembler encounters a parallel
-instruction who
es
components both use the same execution pipeline.
+instruction who
se
components both use the same execution pipeline.
@item Instructions write to the same destination register.
This message is produced when the assembler encounters a parallel
@item Instructions write to the same destination register.
This message is produced when the assembler encounters a parallel
@@
-351,8
+349,8
@@
instruction where both components attempt to modify the same register.
For example these code fragments will produce this message:
@samp{mv r1, r2 || neg r1, r3}
@samp{jl r0 || mv r14, r1}
For example these code fragments will produce this message:
@samp{mv r1, r2 || neg r1, r3}
@samp{jl r0 || mv r14, r1}
-@samp{st r2, @@-r1 || mv r1, r3}
-@samp{mv r1, r2 || ld r0, @@r1+}
+@samp{st r2, @@-r1 || mv r1, r3}
+@samp{mv r1, r2 || ld r0, @@r1+}
@samp{cmp r1, r2 || addx r3, r4} (Both write to the condition bit)
@end table
@samp{cmp r1, r2 || addx r3, r4} (Both write to the condition bit)
@end table
This page took
0.031556 seconds
and
4
git commands to generate.