-/* Used by simulator. */
-int display_pipeline_p;
-int cpu_timer;
-/* This one must have the same type as used in the emulator.
- It's currently an enum so this should be ok for now. */
-int debug_pipeline_p;
-
-#define ARC_CALL_SAVED_REG(r) ((r) >= 16 && (r) < 24)
-
-#define OPMASK 0xf8000000
-
-/* Instruction field accessor macros.
- See the Programmer's Reference Manual. */
-#define X_OP(i) (((i) >> 27) & 0x1f)
-#define X_A(i) (((i) >> 21) & 0x3f)
-#define X_B(i) (((i) >> 15) & 0x3f)
-#define X_C(i) (((i) >> 9) & 0x3f)
-#define X_D(i) ((((i) & 0x1ff) ^ 0x100) - 0x100)
-#define X_L(i) (((((i) >> 5) & 0x3ffffc) ^ 0x200000) - 0x200000)
-#define X_N(i) (((i) >> 5) & 3)
-#define X_Q(i) ((i) & 0x1f)
-
-/* Return non-zero if X is a short immediate data indicator. */
-#define SHIMM_P(x) ((x) == 61 || (x) == 63)
-
-/* Return non-zero if X is a "long" (32 bit) immediate data indicator. */
-#define LIMM_P(x) ((x) == 62)
-
-/* Build a simple instruction. */
-#define BUILD_INSN(op, a, b, c, d) \
- ((((op) & 31) << 27) \
- | (((a) & 63) << 21) \
- | (((b) & 63) << 15) \
- | (((c) & 63) << 9) \
- | ((d) & 511))
-\f
-/* Codestream stuff. */
-static void codestream_read (unsigned int *, int);
-static void codestream_seek (CORE_ADDR);
-static unsigned int codestream_fill (int);
-
-#define CODESTREAM_BUFSIZ 16
-static CORE_ADDR codestream_next_addr;
-static CORE_ADDR codestream_addr;
-/* FIXME assumes sizeof (int) == 32? */
-static unsigned int codestream_buf[CODESTREAM_BUFSIZ];
-static int codestream_off;
-static int codestream_cnt;
-
-#define codestream_tell() \
- (codestream_addr + codestream_off * sizeof (codestream_buf[0]))
-#define codestream_peek() \
- (codestream_cnt == 0 \
- ? codestream_fill (1) \
- : codestream_buf[codestream_off])
-#define codestream_get() \
- (codestream_cnt-- == 0 \
- ? codestream_fill (0) \
- : codestream_buf[codestream_off++])
-
-static unsigned int
-codestream_fill (peek_flag)
- int peek_flag;
-{
- codestream_addr = codestream_next_addr;
- codestream_next_addr += CODESTREAM_BUFSIZ * sizeof (codestream_buf[0]);
- codestream_off = 0;
- codestream_cnt = CODESTREAM_BUFSIZ;
- read_memory (codestream_addr, (char *) codestream_buf,
- CODESTREAM_BUFSIZ * sizeof (codestream_buf[0]));
- /* FIXME: check return code? */
-
-
- /* Handle byte order differences -> convert to host byte ordering. */
- {
- int i;
- for (i = 0; i < CODESTREAM_BUFSIZ; i++)
- codestream_buf[i] =
- extract_unsigned_integer (&codestream_buf[i],
- sizeof (codestream_buf[i]));
- }
-
- if (peek_flag)
- return codestream_peek ();
- else
- return codestream_get ();
+/* Global debug flag. */
+
+int arc_debug;
+
+/* List of "maintenance print arc" commands. */
+
+static struct cmd_list_element *maintenance_print_arc_list = NULL;
+
+/* XML target description features. */
+
+static const char core_v2_feature_name[] = "org.gnu.gdb.arc.core.v2";
+static const char
+ core_reduced_v2_feature_name[] = "org.gnu.gdb.arc.core-reduced.v2";
+static const char
+ core_arcompact_feature_name[] = "org.gnu.gdb.arc.core.arcompact";
+static const char aux_minimal_feature_name[] = "org.gnu.gdb.arc.aux-minimal";
+
+/* XML target description known registers. */
+
+static const char *const core_v2_register_names[] = {
+ "r0", "r1", "r2", "r3",
+ "r4", "r5", "r6", "r7",
+ "r8", "r9", "r10", "r11",
+ "r12", "r13", "r14", "r15",
+ "r16", "r17", "r18", "r19",
+ "r20", "r21", "r22", "r23",
+ "r24", "r25", "gp", "fp",
+ "sp", "ilink", "r30", "blink",
+ "r32", "r33", "r34", "r35",
+ "r36", "r37", "r38", "r39",
+ "r40", "r41", "r42", "r43",
+ "r44", "r45", "r46", "r47",
+ "r48", "r49", "r50", "r51",
+ "r52", "r53", "r54", "r55",
+ "r56", "r57", "accl", "acch",
+ "lp_count", "reserved", "limm", "pcl",
+};
+
+static const char *const aux_minimal_register_names[] = {
+ "pc", "status32",
+};
+
+static const char *const core_arcompact_register_names[] = {
+ "r0", "r1", "r2", "r3",
+ "r4", "r5", "r6", "r7",
+ "r8", "r9", "r10", "r11",
+ "r12", "r13", "r14", "r15",
+ "r16", "r17", "r18", "r19",
+ "r20", "r21", "r22", "r23",
+ "r24", "r25", "gp", "fp",
+ "sp", "ilink1", "ilink2", "blink",
+ "r32", "r33", "r34", "r35",
+ "r36", "r37", "r38", "r39",
+ "r40", "r41", "r42", "r43",
+ "r44", "r45", "r46", "r47",
+ "r48", "r49", "r50", "r51",
+ "r52", "r53", "r54", "r55",
+ "r56", "r57", "r58", "r59",
+ "lp_count", "reserved", "limm", "pcl",
+};
+
+static char *arc_disassembler_options = NULL;
+
+/* Functions are sorted in the order as they are used in the
+ _initialize_arc_tdep (), which uses the same order as gdbarch.h. Static
+ functions are defined before the first invocation. */
+
+/* Returns an unsigned value of OPERAND_NUM in instruction INSN.
+ For relative branch instructions returned value is an offset, not an actual
+ branch target. */
+
+static ULONGEST
+arc_insn_get_operand_value (const struct arc_instruction &insn,
+ unsigned int operand_num)
+{
+ switch (insn.operands[operand_num].kind)
+ {
+ case ARC_OPERAND_KIND_LIMM:
+ gdb_assert (insn.limm_p);
+ return insn.limm_value;
+ case ARC_OPERAND_KIND_SHIMM:
+ return insn.operands[operand_num].value;
+ default:
+ /* Value in instruction is a register number. */
+ struct regcache *regcache = get_current_regcache ();
+ ULONGEST value;
+ regcache_cooked_read_unsigned (regcache,
+ insn.operands[operand_num].value,
+ &value);
+ return value;
+ }