* object.h (Relobj::local_symbol_value): New function.

[deliverable/binutils-gdb.git] / gdb / arm-tdep.h

diff --git a/gdb/arm-tdep.h b/gdb/arm-tdep.h
index a5fc99df5b4a9d2fffc9d0040c515b22eb6901a8..b3a3850987eaca542c95e2c0056e671794ef5645 100644 (file)
--- a/gdb/arm-tdep.h
+++ b/gdb/arm-tdep.h
@@ -1,11 +1,12 @@
 /* Common target dependent code for GDB on ARM systems.
 /* Common target dependent code for GDB on ARM systems.

-   Copyright (C) 2002, 2003 Free Software Foundation, Inc.
+   Copyright (C) 2002, 2003, 2007, 2008, 2009, 2010, 2011
+   Free Software Foundation, Inc.

 
    This file is part of GDB.
 
    This program is free software; you can redistribute it and/or modify
    it under the terms of the GNU General Public License as published by
 
    This file is part of GDB.
 
    This program is free software; you can redistribute it and/or modify
    it under the terms of the GNU General Public License as published by

-   the Free Software Foundation; either version 2 of the License, or
+   the Free Software Foundation; either version 3 of the License, or

    (at your option) any later version.
 
    This program is distributed in the hope that it will be useful,
    (at your option) any later version.
 
    This program is distributed in the hope that it will be useful,


@@ -14,9 +15,7 @@
    GNU General Public License for more details.
 
    You should have received a copy of the GNU General Public License
    GNU General Public License for more details.
 
    You should have received a copy of the GNU General Public License

-   along with this program; if not, write to the Free Software
-   Foundation, Inc., 51 Franklin Street, Fifth Floor,
-   Boston, MA 02110-1301, USA.  */
+   along with this program.  If not, see <http://www.gnu.org/licenses/>.  */

 
 #ifndef ARM_TDEP_H
 #define ARM_TDEP_H
 
 #ifndef ARM_TDEP_H
 #define ARM_TDEP_H


@@ -24,18 +23,15 @@
 /* Forward declarations.  */
 struct gdbarch;
 struct regset;
 /* Forward declarations.  */
 struct gdbarch;
 struct regset;

+struct address_space;

 
 

-/* Register numbers of various important registers.  Note that some of
-   these values are "real" register numbers, and correspond to the
-   general registers of the machine, and some are "phony" register
-   numbers which are too large to be actual register numbers as far as
-   the user is concerned but do serve to get the desired values when
-   passed to read_register.  */
+/* Register numbers of various important registers.  */

 
 enum gdb_regnum {
   ARM_A1_REGNUM = 0,           /* first integer-like argument */
   ARM_A4_REGNUM = 3,           /* last integer-like argument */
   ARM_AP_REGNUM = 11,
 
 enum gdb_regnum {
   ARM_A1_REGNUM = 0,           /* first integer-like argument */
   ARM_A4_REGNUM = 3,           /* last integer-like argument */
   ARM_AP_REGNUM = 11,

+  ARM_IP_REGNUM = 12,

   ARM_SP_REGNUM = 13,          /* Contains address of top of stack */
   ARM_LR_REGNUM = 14,          /* address to return to from a function call */
   ARM_PC_REGNUM = 15,          /* Contains program counter */
   ARM_SP_REGNUM = 13,          /* Contains address of top of stack */
   ARM_LR_REGNUM = 14,          /* address to return to from a function call */
   ARM_PC_REGNUM = 15,          /* Contains program counter */


@@ -44,6 +40,22 @@ enum gdb_regnum {
   ARM_F7_REGNUM = 23,          /* last floating point register */
   ARM_FPS_REGNUM = 24,         /* floating point status register */
   ARM_PS_REGNUM = 25,          /* Contains processor status */
   ARM_F7_REGNUM = 23,          /* last floating point register */
   ARM_FPS_REGNUM = 24,         /* floating point status register */
   ARM_PS_REGNUM = 25,          /* Contains processor status */

+  ARM_WR0_REGNUM,              /* WMMX data registers.  */
+  ARM_WR15_REGNUM = ARM_WR0_REGNUM + 15,
+  ARM_WC0_REGNUM,              /* WMMX control registers.  */
+  ARM_WCSSF_REGNUM = ARM_WC0_REGNUM + 2,
+  ARM_WCASF_REGNUM = ARM_WC0_REGNUM + 3,
+  ARM_WC7_REGNUM = ARM_WC0_REGNUM + 7,
+  ARM_WCGR0_REGNUM,            /* WMMX general purpose registers.  */
+  ARM_WCGR3_REGNUM = ARM_WCGR0_REGNUM + 3,
+  ARM_WCGR7_REGNUM = ARM_WCGR0_REGNUM + 7,
+  ARM_D0_REGNUM,               /* VFP double-precision registers.  */
+  ARM_D31_REGNUM = ARM_D0_REGNUM + 31,
+  ARM_FPSCR_REGNUM,
+
+  ARM_NUM_REGS,
+
+  /* Other useful registers.  */

   ARM_FP_REGNUM = 11,          /* Frame register in ARM code, if used.  */
   THUMB_FP_REGNUM = 7,         /* Frame register in Thumb code, if used.  */
   ARM_NUM_ARG_REGS = 4, 
   ARM_FP_REGNUM = 11,          /* Frame register in ARM code, if used.  */
   THUMB_FP_REGNUM = 7,         /* Frame register in Thumb code, if used.  */
   ARM_NUM_ARG_REGS = 4, 


@@ -60,13 +72,8 @@ enum gdb_regnum {
    bits.  DWORD aligned they use 96 bits.  */
 #define FP_REGISTER_SIZE       12
 
    bits.  DWORD aligned they use 96 bits.  */
 #define FP_REGISTER_SIZE       12
 

-/* Status registers are the same size as general purpose registers.
-   Used for documentation purposes and code readability in this
-   header.  */
-#define STATUS_REGISTER_SIZE   4
-

 /* Number of machine registers.  The only define actually required 
 /* Number of machine registers.  The only define actually required 

-   is NUM_REGS.  The other definitions are used for documentation
+   is gdbarch_num_regs.  The other definitions are used for documentation

    purposes and code readability.  */
 /* For 26 bit ARM code, a fake copy of the PC is placed in register 25 (PS)
    (and called PS for processor status) so the status bits can be cleared
    purposes and code readability.  */
 /* For 26 bit ARM code, a fake copy of the PC is placed in register 25 (PS)
    (and called PS for processor status) so the status bits can be cleared


@@ -100,6 +107,10 @@ enum gdb_regnum {
 #define FLAG_C         0x20000000
 #define FLAG_V         0x10000000
 
 #define FLAG_C         0x20000000
 #define FLAG_V         0x10000000
 

+#define CPSR_T         0x20
+
+#define XPSR_T         0x01000000
+

 /* Type of floating-point code in use by inferior.  There are really 3 models
    that are traditionally supported (plus the endianness issue), but gcc can
    only generate 2 of those.  The third is APCS_FLOAT, where arguments to
 /* Type of floating-point code in use by inferior.  There are really 3 models
    that are traditionally supported (plus the endianness issue), but gcc can
    only generate 2 of those.  The third is APCS_FLOAT, where arguments to


@@ -146,15 +157,32 @@ struct gdbarch_tdep
 
   enum arm_float_model fp_model; /* Floating point calling conventions.  */
 
 
   enum arm_float_model fp_model; /* Floating point calling conventions.  */
 

+  int have_fpa_registers;      /* Does the target report the FPA registers?  */
+  int have_vfp_registers;      /* Does the target report the VFP registers?  */
+  int have_vfp_pseudos;                /* Are we synthesizing the single precision
+                                  VFP registers?  */
+  int have_neon_pseudos;       /* Are we synthesizing the quad precision
+                                  NEON registers?  Requires
+                                  have_vfp_pseudos.  */
+  int have_neon;               /* Do we have a NEON unit?  */
+
+  int is_m;                    /* Does the target follow the "M" profile.  */

   CORE_ADDR lowest_pc;         /* Lowest address at which instructions 
                                   will appear.  */
 
   const char *arm_breakpoint;  /* Breakpoint pattern for an ARM insn.  */
   int arm_breakpoint_size;     /* And its size.  */
   CORE_ADDR lowest_pc;         /* Lowest address at which instructions 
                                   will appear.  */
 
   const char *arm_breakpoint;  /* Breakpoint pattern for an ARM insn.  */
   int arm_breakpoint_size;     /* And its size.  */

-  const char *thumb_breakpoint;        /* Breakpoint pattern for an ARM insn.  */
+  const char *thumb_breakpoint;        /* Breakpoint pattern for a Thumb insn.  */

   int thumb_breakpoint_size;   /* And its size.  */
 
   int thumb_breakpoint_size;   /* And its size.  */
 

-  int jb_pc;                   /* Offset to PC value in jump buffer. 
+  /* If the Thumb breakpoint is an undefined instruction (which is
+     affected by IT blocks) rather than a BKPT instruction (which is
+     not), then we need a 32-bit Thumb breakpoint to preserve the
+     instruction count in IT blocks.  */
+  const char *thumb2_breakpoint;
+  int thumb2_breakpoint_size;
+
+  int jb_pc;                   /* Offset to PC value in jump buffer.

                                   If this is negative, longjmp support
                                   will be disabled.  */
   size_t jb_elt_size;          /* And the size of each entry in the buf.  */
                                   If this is negative, longjmp support
                                   will be disabled.  */
   size_t jb_elt_size;          /* And the size of each entry in the buf.  */


@@ -163,23 +191,145 @@ struct gdbarch_tdep
   enum struct_return struct_return;
 
   /* Cached core file helpers.  */
   enum struct_return struct_return;
 
   /* Cached core file helpers.  */

-  struct regset *gregset, *fpregset;
-};
+  struct regset *gregset, *fpregset, *vfpregset;

 
 

+  /* ISA-specific data types.  */
+  struct type *arm_ext_type;
+  struct type *neon_double_type;
+  struct type *neon_quad_type;

 
 

+  /* Return the expected next PC if FRAME is stopped at a syscall
+     instruction.  */
+  CORE_ADDR (*syscall_next_pc) (struct frame_info *frame);
+};

 
 

-#ifndef LOWEST_PC
-#define LOWEST_PC (gdbarch_tdep (current_gdbarch)->lowest_pc)
-#endif
+/* Structures used for displaced stepping.  */

 
 

-/* Prototypes for internal interfaces needed by more than one MD file.  */
-int arm_pc_is_thumb_dummy (CORE_ADDR);
+/* The maximum number of temporaries available for displaced instructions.  */
+#define DISPLACED_TEMPS                        16
+/* The maximum number of modified instructions generated for one single-stepped
+   instruction, including the breakpoint (usually at the end of the instruction
+   sequence) and any scratch words, etc.  */
+#define DISPLACED_MODIFIED_INSNS       8

 
 

-int arm_pc_is_thumb (CORE_ADDR);
+struct displaced_step_closure
+{
+  ULONGEST tmp[DISPLACED_TEMPS];
+  int rd;
+  int wrote_to_pc;
+  union
+  {
+    struct
+    {
+      int xfersize;
+      int rn;                     /* Writeback register.  */
+      unsigned int immed : 1;      /* Offset is immediate.  */
+      unsigned int writeback : 1;  /* Perform base-register writeback.  */
+      unsigned int restore_r4 : 1; /* Used r4 as scratch.  */
+    } ldst;
+
+    struct
+    {
+      unsigned long dest;
+      unsigned int link : 1;
+      unsigned int exchange : 1;
+      unsigned int cond : 4;
+    } branch;
+
+    struct
+    {
+      unsigned int regmask;
+      int rn;
+      CORE_ADDR xfer_addr;
+      unsigned int load : 1;
+      unsigned int user : 1;
+      unsigned int increment : 1;
+      unsigned int before : 1;
+      unsigned int writeback : 1;
+      unsigned int cond : 4;
+    } block;
+
+    struct
+    {
+      unsigned int immed : 1;
+    } preload;
+
+    struct
+    {
+      /* If non-NULL, override generic SVC handling (e.g. for a particular
+         OS).  */
+      int (*copy_svc_os) (struct gdbarch *gdbarch, struct regcache *regs,
+                         struct displaced_step_closure *dsc);
+    } svc;
+  } u;
+
+  /* The size of original instruction, 2 or 4.  */
+  unsigned int insn_size;
+  /* True if the original insn (and thus all replacement insns) are Thumb
+     instead of ARM.   */
+  unsigned int is_thumb;
+
+  /* The slots in the array is used in this way below,
+     - ARM instruction occupies one slot,
+     - Thumb 16 bit instruction occupies one slot,
+     - Thumb 32-bit instruction occupies *two* slots, one part for each.  */
+  unsigned long modinsn[DISPLACED_MODIFIED_INSNS];
+  int numinsns;
+  CORE_ADDR insn_addr;
+  CORE_ADDR scratch_base;
+  void (*cleanup) (struct gdbarch *, struct regcache *,
+                  struct displaced_step_closure *);
+};
+
+/* Values for the WRITE_PC argument to displaced_write_reg.  If the register
+   write may write to the PC, specifies the way the CPSR T bit, etc. is
+   modified by the instruction.  */

 
 

-CORE_ADDR thumb_get_next_pc (CORE_ADDR);
+enum pc_write_style
+{
+  BRANCH_WRITE_PC,
+  BX_WRITE_PC,
+  LOAD_WRITE_PC,
+  ALU_WRITE_PC,
+  CANNOT_WRITE_PC
+};

 
 

-CORE_ADDR arm_get_next_pc (CORE_ADDR);
+extern void
+  arm_process_displaced_insn (struct gdbarch *gdbarch, CORE_ADDR from,
+                             CORE_ADDR to, struct regcache *regs,
+                             struct displaced_step_closure *dsc);
+extern void
+  arm_displaced_init_closure (struct gdbarch *gdbarch, CORE_ADDR from,
+                             CORE_ADDR to, struct displaced_step_closure *dsc);
+extern ULONGEST
+  displaced_read_reg (struct regcache *regs, struct displaced_step_closure *dsc,
+                     int regno);
+extern void
+  displaced_write_reg (struct regcache *regs,
+                      struct displaced_step_closure *dsc, int regno,
+                      ULONGEST val, enum pc_write_style write_pc);
+
+CORE_ADDR arm_skip_stub (struct frame_info *, CORE_ADDR);
+CORE_ADDR arm_get_next_pc (struct frame_info *, CORE_ADDR);
+void arm_insert_single_step_breakpoint (struct gdbarch *,
+                                       struct address_space *, CORE_ADDR);
+int arm_deal_with_atomic_sequence (struct frame_info *);
+int arm_software_single_step (struct frame_info *);
+int arm_frame_is_thumb (struct frame_info *frame);
+
+extern struct displaced_step_closure *
+  arm_displaced_step_copy_insn (struct gdbarch *, CORE_ADDR, CORE_ADDR,
+                               struct regcache *);
+extern void arm_displaced_step_fixup (struct gdbarch *,
+                                     struct displaced_step_closure *,
+                                     CORE_ADDR, CORE_ADDR, struct regcache *);
+
+/* Return the bit mask in ARM_PS_REGNUM that indicates Thumb mode.  */
+extern int arm_psr_thumb_bit (struct gdbarch *);
+
+/* Is the instruction at the given memory address a Thumb or ARM
+   instruction?  */
+extern int arm_pc_is_thumb (struct gdbarch *, CORE_ADDR);

 
 /* Functions exported from armbsd-tdep.h.  */
 
 
 /* Functions exported from armbsd-tdep.h.  */
 


@@ -190,4 +340,11 @@ extern const struct regset *
   armbsd_regset_from_core_section (struct gdbarch *gdbarch,
                                   const char *sect_name, size_t sect_size);
 
   armbsd_regset_from_core_section (struct gdbarch *gdbarch,
                                   const char *sect_name, size_t sect_size);
 

+/* Target descriptions.  */
+extern struct target_desc *tdesc_arm_with_m;
+extern struct target_desc *tdesc_arm_with_iwmmxt;
+extern struct target_desc *tdesc_arm_with_vfpv2;
+extern struct target_desc *tdesc_arm_with_vfpv3;
+extern struct target_desc *tdesc_arm_with_neon;
+

 #endif /* arm-tdep.h */
 #endif /* arm-tdep.h */