-M:CORE_ADDR:skip_entrypoint:CORE_ADDR ip:ip
-
-f:int:inner_than:CORE_ADDR lhs, CORE_ADDR rhs:lhs, rhs:0:0
-m:const gdb_byte *:breakpoint_from_pc:CORE_ADDR *pcptr, int *lenptr:pcptr, lenptr::0:
-# Return the adjusted address and kind to use for Z0/Z1 packets.
-# KIND is usually the memory length of the breakpoint, but may have a
-# different target-specific meaning.
-m:void:remote_breakpoint_from_pc:CORE_ADDR *pcptr, int *kindptr:pcptr, kindptr:0:default_remote_breakpoint_from_pc::0
-M:CORE_ADDR:adjust_breakpoint_address:CORE_ADDR bpaddr:bpaddr
-m:int:memory_insert_breakpoint:struct bp_target_info *bp_tgt:bp_tgt:0:default_memory_insert_breakpoint::0
-m:int:memory_remove_breakpoint:struct bp_target_info *bp_tgt:bp_tgt:0:default_memory_remove_breakpoint::0
-v:CORE_ADDR:decr_pc_after_break:::0:::0
+M;CORE_ADDR;skip_entrypoint;CORE_ADDR ip;ip
+
+f;int;inner_than;CORE_ADDR lhs, CORE_ADDR rhs;lhs, rhs;0;0
+m;const gdb_byte *;breakpoint_from_pc;CORE_ADDR *pcptr, int *lenptr;pcptr, lenptr;0;default_breakpoint_from_pc;;0
+
+# Return the breakpoint kind for this target based on *PCPTR.
+m;int;breakpoint_kind_from_pc;CORE_ADDR *pcptr;pcptr;;0;
+
+# Return the software breakpoint from KIND. KIND can have target
+# specific meaning like the Z0 kind parameter.
+# SIZE is set to the software breakpoint's length in memory.
+m;const gdb_byte *;sw_breakpoint_from_kind;int kind, int *size;kind, size;;NULL;;0
+
+# Return the breakpoint kind for this target based on the current
+# processor state (e.g. the current instruction mode on ARM) and the
+# *PCPTR. In default, it is gdbarch->breakpoint_kind_from_pc.
+m;int;breakpoint_kind_from_current_state;struct regcache *regcache, CORE_ADDR *pcptr;regcache, pcptr;0;default_breakpoint_kind_from_current_state;;0
+
+M;CORE_ADDR;adjust_breakpoint_address;CORE_ADDR bpaddr;bpaddr
+m;int;memory_insert_breakpoint;struct bp_target_info *bp_tgt;bp_tgt;0;default_memory_insert_breakpoint;;0
+m;int;memory_remove_breakpoint;struct bp_target_info *bp_tgt;bp_tgt;0;default_memory_remove_breakpoint;;0
+v;CORE_ADDR;decr_pc_after_break;;;0;;;0