+ struct gdbarch *arch = get_frame_arch (next_frame);
+
+ if (regnum == HPPA_PCOQ_TAIL_REGNUM)
+ {
+ if (valuep)
+ {
+ int size = register_size (arch, HPPA_PCOQ_HEAD_REGNUM);
+ CORE_ADDR pc;
+
+ trad_frame_get_prev_register (next_frame, saved_regs,
+ HPPA_PCOQ_HEAD_REGNUM, optimizedp,
+ lvalp, addrp, realnump, valuep);
+
+ pc = extract_unsigned_integer (valuep, size);
+ store_unsigned_integer (valuep, size, pc + 4);
+ }
+
+ /* It's a computed value. */
+ *optimizedp = 0;
+ *lvalp = not_lval;
+ *addrp = 0;
+ *realnump = -1;
+ return;
+ }
+
+ /* Make sure the "flags" register is zero in all unwound frames.
+ The "flags" registers is a HP-UX specific wart, and only the code
+ in hppa-hpux-tdep.c depends on it. However, it is easier to deal
+ with it here. This shouldn't affect other systems since those
+ should provide zero for the "flags" register anyway. */
+ if (regnum == HPPA_FLAGS_REGNUM)
+ {
+ if (valuep)
+ store_unsigned_integer (valuep, register_size (arch, regnum), 0);
+
+ /* It's a computed value. */
+ *optimizedp = 0;
+ *lvalp = not_lval;
+ *addrp = 0;
+ *realnump = -1;
+ return;
+ }
+
+ trad_frame_get_prev_register (next_frame, saved_regs, regnum,
+ optimizedp, lvalp, addrp, realnump, valuep);
+}
+\f
+
+/* An instruction to match. */
+struct insn_pattern
+{
+ unsigned int data; /* See if it matches this.... */
+ unsigned int mask; /* ... with this mask. */
+};
+
+/* See bfd/elf32-hppa.c */
+static struct insn_pattern hppa_long_branch_stub[] = {
+ /* ldil LR'xxx,%r1 */
+ { 0x20200000, 0xffe00000 },
+ /* be,n RR'xxx(%sr4,%r1) */
+ { 0xe0202002, 0xffe02002 },
+ { 0, 0 }
+};
+
+static struct insn_pattern hppa_long_branch_pic_stub[] = {
+ /* b,l .+8, %r1 */
+ { 0xe8200000, 0xffe00000 },
+ /* addil LR'xxx - ($PIC_pcrel$0 - 4), %r1 */
+ { 0x28200000, 0xffe00000 },
+ /* be,n RR'xxxx - ($PIC_pcrel$0 - 8)(%sr4, %r1) */
+ { 0xe0202002, 0xffe02002 },
+ { 0, 0 }
+};
+
+static struct insn_pattern hppa_import_stub[] = {
+ /* addil LR'xxx, %dp */
+ { 0x2b600000, 0xffe00000 },
+ /* ldw RR'xxx(%r1), %r21 */
+ { 0x48350000, 0xffffb000 },
+ /* bv %r0(%r21) */
+ { 0xeaa0c000, 0xffffffff },
+ /* ldw RR'xxx+4(%r1), %r19 */
+ { 0x48330000, 0xffffb000 },
+ { 0, 0 }
+};
+
+static struct insn_pattern hppa_import_pic_stub[] = {
+ /* addil LR'xxx,%r19 */
+ { 0x2a600000, 0xffe00000 },
+ /* ldw RR'xxx(%r1),%r21 */
+ { 0x48350000, 0xffffb000 },
+ /* bv %r0(%r21) */
+ { 0xeaa0c000, 0xffffffff },
+ /* ldw RR'xxx+4(%r1),%r19 */
+ { 0x48330000, 0xffffb000 },
+ { 0, 0 },
+};
+
+static struct insn_pattern hppa_plt_stub[] = {
+ /* b,l 1b, %r20 - 1b is 3 insns before here */
+ { 0xea9f1fdd, 0xffffffff },
+ /* depi 0,31,2,%r20 */
+ { 0xd6801c1e, 0xffffffff },
+ { 0, 0 }
+};
+
+static struct insn_pattern hppa_sigtramp[] = {
+ /* ldi 0, %r25 or ldi 1, %r25 */
+ { 0x34190000, 0xfffffffd },
+ /* ldi __NR_rt_sigreturn, %r20 */
+ { 0x3414015a, 0xffffffff },
+ /* be,l 0x100(%sr2, %r0), %sr0, %r31 */
+ { 0xe4008200, 0xffffffff },
+ /* nop */
+ { 0x08000240, 0xffffffff },
+ { 0, 0 }
+};
+
+/* Maximum number of instructions on the patterns above. */
+#define HPPA_MAX_INSN_PATTERN_LEN 4
+
+/* Return non-zero if the instructions at PC match the series
+ described in PATTERN, or zero otherwise. PATTERN is an array of
+ 'struct insn_pattern' objects, terminated by an entry whose mask is
+ zero.
+
+ When the match is successful, fill INSN[i] with what PATTERN[i]
+ matched. */
+
+static int
+hppa_match_insns (CORE_ADDR pc, struct insn_pattern *pattern,
+ unsigned int *insn)
+{
+ CORE_ADDR npc = pc;
+ int i;
+
+ for (i = 0; pattern[i].mask; i++)
+ {
+ gdb_byte buf[HPPA_INSN_SIZE];