+ else if (hppa64_floating_p (type))
+ {
+ if (len > 8)
+ {
+ /* "Quad-precision (128-bit) floating-point scalar
+ parameters are aligned on a 16-byte boundary." */
+ offset = align_up (offset, 16);
+
+ /* "Double-extended- and quad-precision floating-point
+ parameters within the first 64 bytes of the parameter
+ list are always passed in general registers." */
+ }
+ else
+ {
+ if (len == 4)
+ {
+ /* "Single-precision (32-bit) floating-point scalar
+ parameters are padded on the left with 32 bits of
+ garbage (i.e., the floating-point value is in the
+ least-significant 32 bits of a 64-bit storage
+ unit)." */
+ offset += 4;
+ }
+
+ /* "Single- and double-precision floating-point
+ parameters in this area are passed according to the
+ available formal parameter information in a function
+ prototype. [...] If no prototype is in scope,
+ floating-point parameters must be passed both in the
+ corresponding general registers and in the
+ corresponding floating-point registers." */
+ regnum = HPPA64_FP4_REGNUM + offset / 8;
+
+ if (regnum < HPPA64_FP4_REGNUM + 8)
+ {
+ /* "Single-precision floating-point parameters, when
+ passed in floating-point registers, are passed in
+ the right halves of the floating point registers;
+ the left halves are unused." */
+ regcache->cooked_write_part (regnum, offset % 8, len,
+ value_contents (arg));
+ }
+ }
+ }
+ else
+ {
+ if (len > 8)
+ {
+ /* "Aggregates larger than 8 bytes are aligned on a
+ 16-byte boundary, possibly leaving an unused argument
+ slot, which is filled with garbage. If necessary,
+ they are padded on the right (with garbage), to a
+ multiple of 8 bytes." */
+ offset = align_up (offset, 16);
+ }
+ }
+
+ /* If we are passing a function pointer, make sure we pass a function
+ descriptor instead of the function entry address. */
+ if (type->code () == TYPE_CODE_PTR
+ && TYPE_TARGET_TYPE (type)->code () == TYPE_CODE_FUNC)
+ {
+ ULONGEST codeptr, fptr;
+
+ codeptr = unpack_long (type, value_contents (arg));
+ fptr = hppa64_convert_code_addr_to_fptr (gdbarch, codeptr);
+ store_unsigned_integer (fptrbuf, TYPE_LENGTH (type), byte_order,
+ fptr);
+ valbuf = fptrbuf;
+ }
+ else
+ {
+ valbuf = value_contents (arg);
+ }
+
+ /* Always store the argument in memory. */
+ write_memory (sp + offset, valbuf, len);
+
+ regnum = HPPA_ARG0_REGNUM - offset / 8;
+ while (regnum > HPPA_ARG0_REGNUM - 8 && len > 0)
+ {
+ regcache->cooked_write_part (regnum, offset % 8, std::min (len, 8),
+ valbuf);
+ offset += std::min (len, 8);
+ valbuf += std::min (len, 8);
+ len -= std::min (len, 8);
+ regnum--;
+ }
+
+ offset += len;
+ }
+
+ /* Set up GR29 (%ret1) to hold the argument pointer (ap). */
+ regcache_cooked_write_unsigned (regcache, HPPA_RET1_REGNUM, sp + 64);
+
+ /* Allocate the outgoing parameter area. Make sure the outgoing
+ parameter area is multiple of 16 bytes in length. */
+ sp += std::max (align_up (offset, 16), (ULONGEST) 64);
+
+ /* Allocate 32-bytes of scratch space. The documentation doesn't
+ mention this, but it seems to be needed. */
+ sp += 32;
+
+ /* Allocate the frame marker area. */
+ sp += 16;
+
+ /* If a structure has to be returned, set up GR 28 (%ret0) to hold
+ its address. */
+ if (return_method == return_method_struct)
+ regcache_cooked_write_unsigned (regcache, HPPA_RET0_REGNUM, struct_addr);
+
+ /* Set up GR27 (%dp) to hold the global pointer (gp). */
+ gp = tdep->find_global_pointer (gdbarch, function);
+ if (gp != 0)
+ regcache_cooked_write_unsigned (regcache, HPPA_DP_REGNUM, gp);
+
+ /* Set up GR2 (%rp) to hold the return pointer (rp). */
+ if (!gdbarch_push_dummy_code_p (gdbarch))
+ regcache_cooked_write_unsigned (regcache, HPPA_RP_REGNUM, bp_addr);
+
+ /* Set up GR30 to hold the stack pointer (sp). */
+ regcache_cooked_write_unsigned (regcache, HPPA_SP_REGNUM, sp);
+
+ return sp;
+}
+\f
+
+/* Handle 32/64-bit struct return conventions. */
+
+static enum return_value_convention
+hppa32_return_value (struct gdbarch *gdbarch, struct value *function,
+ struct type *type, struct regcache *regcache,
+ gdb_byte *readbuf, const gdb_byte *writebuf)
+{
+ if (TYPE_LENGTH (type) <= 2 * 4)
+ {
+ /* The value always lives in the right hand end of the register
+ (or register pair)? */
+ int b;
+ int reg = type->code () == TYPE_CODE_FLT ? HPPA_FP4_REGNUM : 28;
+ int part = TYPE_LENGTH (type) % 4;
+ /* The left hand register contains only part of the value,
+ transfer that first so that the rest can be xfered as entire
+ 4-byte registers. */
+ if (part > 0)
+ {
+ if (readbuf != NULL)
+ regcache->cooked_read_part (reg, 4 - part, part, readbuf);
+ if (writebuf != NULL)
+ regcache->cooked_write_part (reg, 4 - part, part, writebuf);
+ reg++;
+ }
+ /* Now transfer the remaining register values. */
+ for (b = part; b < TYPE_LENGTH (type); b += 4)
+ {
+ if (readbuf != NULL)
+ regcache->cooked_read (reg, readbuf + b);
+ if (writebuf != NULL)
+ regcache->cooked_write (reg, writebuf + b);
+ reg++;
+ }
+ return RETURN_VALUE_REGISTER_CONVENTION;
+ }
+ else
+ return RETURN_VALUE_STRUCT_CONVENTION;
+}
+
+static enum return_value_convention
+hppa64_return_value (struct gdbarch *gdbarch, struct value *function,
+ struct type *type, struct regcache *regcache,
+ gdb_byte *readbuf, const gdb_byte *writebuf)
+{
+ int len = TYPE_LENGTH (type);
+ int regnum, offset;
+
+ if (len > 16)
+ {
+ /* All return values larger than 128 bits must be aggregate
+ return values. */
+ gdb_assert (!hppa64_integral_or_pointer_p (type));
+ gdb_assert (!hppa64_floating_p (type));
+
+ /* "Aggregate return values larger than 128 bits are returned in
+ a buffer allocated by the caller. The address of the buffer
+ must be passed in GR 28." */
+ return RETURN_VALUE_STRUCT_CONVENTION;
+ }
+
+ if (hppa64_integral_or_pointer_p (type))
+ {
+ /* "Integral return values are returned in GR 28. Values
+ smaller than 64 bits are padded on the left (with garbage)." */
+ regnum = HPPA_RET0_REGNUM;
+ offset = 8 - len;
+ }
+ else if (hppa64_floating_p (type))
+ {
+ if (len > 8)
+ {
+ /* "Double-extended- and quad-precision floating-point
+ values are returned in GRs 28 and 29. The sign,
+ exponent, and most-significant bits of the mantissa are
+ returned in GR 28; the least-significant bits of the
+ mantissa are passed in GR 29. For double-extended
+ precision values, GR 29 is padded on the right with 48
+ bits of garbage." */
+ regnum = HPPA_RET0_REGNUM;
+ offset = 0;
+ }
+ else
+ {
+ /* "Single-precision and double-precision floating-point
+ return values are returned in FR 4R (single precision) or
+ FR 4 (double-precision)." */
+ regnum = HPPA64_FP4_REGNUM;
+ offset = 8 - len;
+ }
+ }
+ else
+ {
+ /* "Aggregate return values up to 64 bits in size are returned
+ in GR 28. Aggregates smaller than 64 bits are left aligned
+ in the register; the pad bits on the right are undefined."
+
+ "Aggregate return values between 65 and 128 bits are returned
+ in GRs 28 and 29. The first 64 bits are placed in GR 28, and
+ the remaining bits are placed, left aligned, in GR 29. The
+ pad bits on the right of GR 29 (if any) are undefined." */
+ regnum = HPPA_RET0_REGNUM;
+ offset = 0;
+ }
+
+ if (readbuf)
+ {
+ while (len > 0)
+ {
+ regcache->cooked_read_part (regnum, offset, std::min (len, 8),
+ readbuf);
+ readbuf += std::min (len, 8);
+ len -= std::min (len, 8);
+ regnum++;
+ }
+ }
+
+ if (writebuf)
+ {
+ while (len > 0)
+ {
+ regcache->cooked_write_part (regnum, offset, std::min (len, 8),
+ writebuf);
+ writebuf += std::min (len, 8);
+ len -= std::min (len, 8);
+ regnum++;
+ }
+ }
+
+ return RETURN_VALUE_REGISTER_CONVENTION;
+}
+\f
+
+static CORE_ADDR
+hppa32_convert_from_func_ptr_addr (struct gdbarch *gdbarch, CORE_ADDR addr,
+ struct target_ops *targ)
+{
+ if (addr & 2)
+ {
+ struct type *func_ptr_type = builtin_type (gdbarch)->builtin_func_ptr;
+ CORE_ADDR plabel = addr & ~3;
+ return read_memory_typed_address (plabel, func_ptr_type);
+ }
+
+ return addr;
+}
+
+static CORE_ADDR
+hppa32_frame_align (struct gdbarch *gdbarch, CORE_ADDR addr)
+{
+ /* HP frames are 64-byte (or cache line) aligned (yes that's _byte_
+ and not _bit_)! */
+ return align_up (addr, 64);
+}
+
+/* Force all frames to 16-byte alignment. Better safe than sorry. */
+
+static CORE_ADDR
+hppa64_frame_align (struct gdbarch *gdbarch, CORE_ADDR addr)
+{
+ /* Just always 16-byte align. */
+ return align_up (addr, 16);
+}
+
+static CORE_ADDR
+hppa_read_pc (readable_regcache *regcache)
+{
+ ULONGEST ipsw;
+ ULONGEST pc;
+
+ regcache->cooked_read (HPPA_IPSW_REGNUM, &ipsw);
+ regcache->cooked_read (HPPA_PCOQ_HEAD_REGNUM, &pc);
+
+ /* If the current instruction is nullified, then we are effectively
+ still executing the previous instruction. Pretend we are still
+ there. This is needed when single stepping; if the nullified
+ instruction is on a different line, we don't want GDB to think
+ we've stepped onto that line. */
+ if (ipsw & 0x00200000)
+ pc -= 4;
+
+ return pc & ~0x3;
+}
+
+void
+hppa_write_pc (struct regcache *regcache, CORE_ADDR pc)
+{
+ regcache_cooked_write_unsigned (regcache, HPPA_PCOQ_HEAD_REGNUM, pc);
+ regcache_cooked_write_unsigned (regcache, HPPA_PCOQ_TAIL_REGNUM, pc + 4);
+}
+