+#include "inf-ptrace.h"
+
+class ia64_linux_nat_target final : public linux_nat_target
+{
+public:
+ /* Add our register access methods. */
+ void fetch_registers (struct regcache *, int) override;
+ void store_registers (struct regcache *, int) override;
+
+ enum target_xfer_status xfer_partial (enum target_object object,
+ const char *annex,
+ gdb_byte *readbuf,
+ const gdb_byte *writebuf,
+ ULONGEST offset, ULONGEST len,
+ ULONGEST *xfered_len) override;
+
+ /* Override watchpoint routines. */
+
+ /* The IA-64 architecture can step over a watch point (without
+ triggering it again) if the "dd" (data debug fault disable) bit
+ in the processor status word is set.
+
+ This PSR bit is set in
+ ia64_linux_nat_target::stopped_by_watchpoint when the code there
+ has determined that a hardware watchpoint has indeed been hit.
+ The CPU will then be able to execute one instruction without
+ triggering a watchpoint. */
+ bool have_steppable_watchpoint () override { return true; }
+
+ int can_use_hw_breakpoint (enum bptype, int, int) override;
+ bool stopped_by_watchpoint () override;
+ bool stopped_data_address (CORE_ADDR *) override;
+ int insert_watchpoint (CORE_ADDR, int, enum target_hw_bp_type,
+ struct expression *) override;
+ int remove_watchpoint (CORE_ADDR, int, enum target_hw_bp_type,
+ struct expression *) override;
+ /* Override linux_nat_target low methods. */
+ void low_new_thread (struct lwp_info *lp) override;
+ bool low_status_is_event (int status) override;
+
+ void enable_watchpoints_in_psr (ptid_t ptid);
+};
+
+static ia64_linux_nat_target the_ia64_linux_nat_target;
+