+ struct gdbarch *gdbarch = regcache->arch ();
+ CORE_ADDR addr;
+ gdb_byte buf[4];
+ uint16_t inst;
+ uint32_t tmpu32;
+ ULONGEST fp;
+ enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
+ std::vector<CORE_ADDR> next_pcs;
+
+ addr = regcache_read_pc (regcache);
+
+ inst = (uint16_t) moxie_process_readu (addr, buf, 2, byte_order);
+
+ /* Decode instruction. */
+ if (inst & (1 << 15))
+ {
+ if (inst & (1 << 14))
+ {
+ /* This is a Form 3 instruction. */
+ int opcode = (inst >> 10 & 0xf);
+
+ switch (opcode)
+ {
+ case 0x00: /* beq */
+ case 0x01: /* bne */
+ case 0x02: /* blt */
+ case 0x03: /* bgt */
+ case 0x04: /* bltu */
+ case 0x05: /* bgtu */
+ case 0x06: /* bge */
+ case 0x07: /* ble */
+ case 0x08: /* bgeu */
+ case 0x09: /* bleu */
+ /* Insert breaks on both branches, because we can't currently tell
+ which way things will go. */
+ next_pcs.push_back (addr + 2);
+ next_pcs.push_back (addr + 2 + INST2OFFSET(inst));
+ break;
+ default:
+ {
+ /* Do nothing. */
+ break;
+ }
+ }
+ }
+ else
+ {
+ /* This is a Form 2 instruction. They are all 16 bits. */
+ next_pcs.push_back (addr + 2);
+ }
+ }
+ else
+ {
+ /* This is a Form 1 instruction. */
+ int opcode = inst >> 8;
+
+ switch (opcode)
+ {
+ /* 16-bit instructions. */
+ case 0x00: /* bad */
+ case 0x02: /* mov (register-to-register) */
+ case 0x05: /* add.l */
+ case 0x06: /* push */
+ case 0x07: /* pop */
+ case 0x0a: /* ld.l (register indirect) */
+ case 0x0b: /* st.l */
+ case 0x0e: /* cmp */
+ case 0x0f: /* nop */
+ case 0x10: /* sex.b */
+ case 0x11: /* sex.s */
+ case 0x12: /* zex.b */
+ case 0x13: /* zex.s */
+ case 0x14: /* umul.x */
+ case 0x15: /* mul.x */
+ case 0x16:
+ case 0x17:
+ case 0x18:
+ case 0x1c: /* ld.b (register indirect) */
+ case 0x1e: /* st.b */
+ case 0x21: /* ld.s (register indirect) */
+ case 0x23: /* st.s */
+ case 0x26: /* and */
+ case 0x27: /* lshr */
+ case 0x28: /* ashl */
+ case 0x29: /* sub.l */
+ case 0x2a: /* neg */
+ case 0x2b: /* or */
+ case 0x2c: /* not */
+ case 0x2d: /* ashr */
+ case 0x2e: /* xor */
+ case 0x2f: /* mul.l */
+ case 0x31: /* div.l */
+ case 0x32: /* udiv.l */
+ case 0x33: /* mod.l */
+ case 0x34: /* umod.l */
+ next_pcs.push_back (addr + 2);
+ break;
+
+ /* 32-bit instructions. */
+ case 0x0c: /* ldo.l */
+ case 0x0d: /* sto.l */
+ case 0x36: /* ldo.b */
+ case 0x37: /* sto.b */
+ case 0x38: /* ldo.s */
+ case 0x39: /* sto.s */
+ next_pcs.push_back (addr + 4);
+ break;
+
+ /* 48-bit instructions. */
+ case 0x01: /* ldi.l (immediate) */
+ case 0x08: /* lda.l */
+ case 0x09: /* sta.l */
+ case 0x1b: /* ldi.b (immediate) */
+ case 0x1d: /* lda.b */
+ case 0x1f: /* sta.b */
+ case 0x20: /* ldi.s (immediate) */
+ case 0x22: /* lda.s */
+ case 0x24: /* sta.s */
+ next_pcs.push_back (addr + 6);
+ break;
+
+ /* Control flow instructions. */
+ case 0x03: /* jsra */
+ case 0x1a: /* jmpa */
+ next_pcs.push_back (moxie_process_readu (addr + 2, buf, 4,
+ byte_order));
+ break;
+
+ case 0x04: /* ret */
+ regcache_cooked_read_unsigned (regcache, MOXIE_FP_REGNUM, &fp);
+ next_pcs.push_back (moxie_process_readu (fp + 4, buf, 4, byte_order));
+ break;
+
+ case 0x19: /* jsr */
+ case 0x25: /* jmp */
+ regcache->raw_read ((inst >> 4) & 0xf, (gdb_byte *) & tmpu32);
+ next_pcs.push_back (tmpu32);
+ break;
+
+ case 0x30: /* swi */
+ case 0x35: /* brk */
+ /* Unsupported, for now. */
+ break;
+ }
+ }
+
+ return next_pcs;