+/* Return non-zero if the target is capable of using hardware to evaluate
+ the condition expression, thus only triggering the watchpoint when it is
+ true. */
+bool
+ppc_linux_nat_target::can_accel_watchpoint_condition (CORE_ADDR addr, int len,
+ int rw,
+ struct expression *cond)
+{
+ CORE_ADDR data_value;
+
+ return (have_ptrace_hwdebug_interface ()
+ && hwdebug_info.num_condition_regs > 0
+ && check_condition (addr, cond, &data_value, &len));
+}
+
+/* Set up P with the parameters necessary to request a watchpoint covering
+ LEN bytes starting at ADDR and if possible with condition expression COND
+ evaluated by hardware. INSERT tells if we are creating a request for
+ inserting or removing the watchpoint. */
+
+static void
+create_watchpoint_request (struct ppc_hw_breakpoint *p, CORE_ADDR addr,
+ int len, enum target_hw_bp_type type,
+ struct expression *cond, int insert)
+{
+ if (len == 1
+ || !(hwdebug_info.features & PPC_DEBUG_FEATURE_DATA_BP_RANGE))
+ {
+ int use_condition;
+ CORE_ADDR data_value;
+
+ use_condition = (insert? can_use_watchpoint_cond_accel ()
+ : hwdebug_info.num_condition_regs > 0);
+ if (cond && use_condition && check_condition (addr, cond,
+ &data_value, &len))
+ calculate_dvc (addr, len, data_value, &p->condition_mode,
+ &p->condition_value);
+ else
+ {
+ p->condition_mode = PPC_BREAKPOINT_CONDITION_NONE;
+ p->condition_value = 0;
+ }
+
+ p->addr_mode = PPC_BREAKPOINT_MODE_EXACT;
+ p->addr2 = 0;
+ }
+ else
+ {
+ p->addr_mode = PPC_BREAKPOINT_MODE_RANGE_INCLUSIVE;
+ p->condition_mode = PPC_BREAKPOINT_CONDITION_NONE;
+ p->condition_value = 0;
+
+ /* The watchpoint will trigger if the address of the memory access is
+ within the defined range, as follows: p->addr <= address < p->addr2.
+
+ Note that the above sentence just documents how ptrace interprets
+ its arguments; the watchpoint is set to watch the range defined by
+ the user _inclusively_, as specified by the user interface. */
+ p->addr2 = (uint64_t) addr + len;
+ }
+
+ p->version = PPC_DEBUG_CURRENT_VERSION;
+ p->trigger_type = get_trigger_type (type);
+ p->addr = (uint64_t) addr;
+}
+
+int
+ppc_linux_nat_target::insert_watchpoint (CORE_ADDR addr, int len,
+ enum target_hw_bp_type type,
+ struct expression *cond)
+{
+ struct lwp_info *lp;
+ int ret = -1;
+
+ if (have_ptrace_hwdebug_interface ())
+ {
+ struct ppc_hw_breakpoint p;
+
+ create_watchpoint_request (&p, addr, len, type, cond, 1);
+
+ ALL_LWPS (lp)
+ hwdebug_insert_point (&p, lp->ptid.lwp ());
+
+ ret = 0;
+ }
+ else
+ {
+ long dabr_value;
+ long read_mode, write_mode;
+
+ if (linux_get_hwcap (current_top_target ()) & PPC_FEATURE_BOOKE)
+ {
+ /* PowerPC 440 requires only the read/write flags to be passed
+ to the kernel. */
+ read_mode = 1;
+ write_mode = 2;
+ }
+ else
+ {
+ /* PowerPC 970 and other DABR-based processors are required to pass
+ the Breakpoint Translation bit together with the flags. */
+ read_mode = 5;
+ write_mode = 6;
+ }
+
+ dabr_value = addr & ~(read_mode | write_mode);
+ switch (type)
+ {
+ case hw_read:
+ /* Set read and translate bits. */
+ dabr_value |= read_mode;
+ break;
+ case hw_write:
+ /* Set write and translate bits. */
+ dabr_value |= write_mode;
+ break;
+ case hw_access:
+ /* Set read, write and translate bits. */
+ dabr_value |= read_mode | write_mode;
+ break;
+ }
+
+ saved_dabr_value = dabr_value;
+
+ ALL_LWPS (lp)
+ if (ptrace (PTRACE_SET_DEBUGREG, lp->ptid.lwp (), 0,
+ saved_dabr_value) < 0)
+ return -1;
+
+ ret = 0;
+ }
+
+ return ret;
+}
+
+int
+ppc_linux_nat_target::remove_watchpoint (CORE_ADDR addr, int len,
+ enum target_hw_bp_type type,
+ struct expression *cond)
+{
+ struct lwp_info *lp;
+ int ret = -1;
+
+ if (have_ptrace_hwdebug_interface ())
+ {
+ struct ppc_hw_breakpoint p;
+
+ create_watchpoint_request (&p, addr, len, type, cond, 0);
+
+ ALL_LWPS (lp)
+ hwdebug_remove_point (&p, lp->ptid.lwp ());
+
+ ret = 0;
+ }
+ else
+ {
+ saved_dabr_value = 0;
+ ALL_LWPS (lp)
+ if (ptrace (PTRACE_SET_DEBUGREG, lp->ptid.lwp (), 0,
+ saved_dabr_value) < 0)
+ return -1;
+
+ ret = 0;
+ }
+
+ return ret;
+}
+
+void
+ppc_linux_nat_target::low_new_thread (struct lwp_info *lp)
+{
+ int tid = lp->ptid.lwp ();
+
+ if (have_ptrace_hwdebug_interface ())
+ {
+ int i;
+ struct thread_points *p;
+ struct hw_break_tuple *hw_breaks;
+
+ if (ppc_threads.empty ())
+ return;
+
+ /* Get a list of breakpoints from any thread. */
+ p = ppc_threads.back ();
+ hw_breaks = p->hw_breaks;
+
+ /* Copy that thread's breakpoints and watchpoints to the new thread. */
+ for (i = 0; i < max_slots_number; i++)
+ if (hw_breaks[i].hw_break)
+ {
+ /* Older kernels did not make new threads inherit their parent
+ thread's debug state, so we always clear the slot and replicate
+ the debug state ourselves, ensuring compatibility with all
+ kernels. */
+
+ /* The ppc debug resource accounting is done through "slots".
+ Ask the kernel the deallocate this specific *point's slot. */
+ ptrace (PPC_PTRACE_DELHWDEBUG, tid, 0, hw_breaks[i].slot);
+
+ hwdebug_insert_point (hw_breaks[i].hw_break, tid);
+ }
+ }
+ else
+ ptrace (PTRACE_SET_DEBUGREG, tid, 0, saved_dabr_value);
+}
+
+static void
+ppc_linux_thread_exit (struct thread_info *tp, int silent)
+{
+ int i;
+ int tid = tp->ptid.lwp ();
+ struct hw_break_tuple *hw_breaks;
+ struct thread_points *t = NULL;
+
+ if (!have_ptrace_hwdebug_interface ())
+ return;
+
+ for (i = 0; i < ppc_threads.size (); i++)
+ {
+ if (ppc_threads[i]->tid == tid)
+ {
+ t = ppc_threads[i];
+ break;
+ }
+ }
+
+ if (t == NULL)
+ return;
+
+ unordered_remove (ppc_threads, i);
+
+ hw_breaks = t->hw_breaks;
+
+ for (i = 0; i < max_slots_number; i++)
+ if (hw_breaks[i].hw_break)
+ xfree (hw_breaks[i].hw_break);
+
+ xfree (t->hw_breaks);
+ xfree (t);
+}
+
+bool
+ppc_linux_nat_target::stopped_data_address (CORE_ADDR *addr_p)
+{
+ siginfo_t siginfo;
+
+ if (!linux_nat_get_siginfo (inferior_ptid, &siginfo))
+ return false;
+
+ if (siginfo.si_signo != SIGTRAP
+ || (siginfo.si_code & 0xffff) != 0x0004 /* TRAP_HWBKPT */)
+ return false;
+
+ if (have_ptrace_hwdebug_interface ())
+ {
+ int i;
+ struct thread_points *t;
+ struct hw_break_tuple *hw_breaks;
+ /* The index (or slot) of the *point is passed in the si_errno field. */
+ int slot = siginfo.si_errno;
+
+ t = hwdebug_find_thread_points_by_tid (inferior_ptid.lwp (), 0);
+
+ /* Find out if this *point is a hardware breakpoint.
+ If so, we should return 0. */
+ if (t)
+ {
+ hw_breaks = t->hw_breaks;
+ for (i = 0; i < max_slots_number; i++)
+ if (hw_breaks[i].hw_break && hw_breaks[i].slot == slot
+ && hw_breaks[i].hw_break->trigger_type
+ == PPC_BREAKPOINT_TRIGGER_EXECUTE)
+ return false;
+ }
+ }
+
+ *addr_p = (CORE_ADDR) (uintptr_t) siginfo.si_addr;
+ return true;
+}
+
+bool
+ppc_linux_nat_target::stopped_by_watchpoint ()