+ struct value *arg = args[argno];
+ struct type *type = check_typedef (value_type (arg));
+ int len = TYPE_LENGTH (type);
+ const bfd_byte *val = value_contents (arg);
+
+ if (TYPE_CODE (type) == TYPE_CODE_FLT && len <= 8
+ && !tdep->soft_float)
+ {
+ /* Floating point value converted to "double" then
+ passed in an FP register, when the registers run out,
+ 8 byte aligned stack is used. */
+ if (freg <= 8)
+ {
+ if (write_pass)
+ {
+ /* Always store the floating point value using
+ the register's floating-point format. */
+ gdb_byte regval[MAX_REGISTER_SIZE];
+ struct type *regtype
+ = register_type (gdbarch, tdep->ppc_fp0_regnum + freg);
+ convert_typed_floating (val, type, regval, regtype);
+ regcache_cooked_write (regcache,
+ tdep->ppc_fp0_regnum + freg,
+ regval);
+ }
+ freg++;
+ }
+ else
+ {
+ /* The SysV ABI tells us to convert floats to
+ doubles before writing them to an 8 byte aligned
+ stack location. Unfortunately GCC does not do
+ that, and stores floats into 4 byte aligned
+ locations without converting them to doubles.
+ Since there is no know compiler that actually
+ follows the ABI here, we implement the GCC
+ convention. */
+
+ /* Align to 4 bytes or 8 bytes depending on the type of
+ the argument (float or double). */
+ argoffset = align_up (argoffset, len);
+ if (write_pass)
+ write_memory (sp + argoffset, val, len);
+ argoffset += len;
+ }
+ }
+ else if (TYPE_CODE (type) == TYPE_CODE_FLT
+ && len == 16
+ && !tdep->soft_float
+ && (gdbarch_long_double_format (gdbarch)
+ == floatformats_ibm_long_double))
+ {
+ /* IBM long double passed in two FP registers if
+ available, otherwise 8-byte aligned stack. */
+ if (freg <= 7)
+ {
+ if (write_pass)
+ {
+ regcache_cooked_write (regcache,
+ tdep->ppc_fp0_regnum + freg,
+ val);
+ regcache_cooked_write (regcache,
+ tdep->ppc_fp0_regnum + freg + 1,
+ val + 8);
+ }
+ freg += 2;
+ }
+ else
+ {
+ argoffset = align_up (argoffset, 8);
+ if (write_pass)
+ write_memory (sp + argoffset, val, len);
+ argoffset += 16;
+ }
+ }
+ else if (len == 8
+ && (TYPE_CODE (type) == TYPE_CODE_INT /* long long */
+ || TYPE_CODE (type) == TYPE_CODE_FLT /* double */
+ || (TYPE_CODE (type) == TYPE_CODE_DECFLOAT
+ && tdep->soft_float)))
+ {
+ /* "long long" or soft-float "double" or "_Decimal64"
+ passed in an odd/even register pair with the low
+ addressed word in the odd register and the high
+ addressed word in the even register, or when the
+ registers run out an 8 byte aligned stack
+ location. */
+ if (greg > 9)
+ {
+ /* Just in case GREG was 10. */
+ greg = 11;
+ argoffset = align_up (argoffset, 8);
+ if (write_pass)
+ write_memory (sp + argoffset, val, len);
+ argoffset += 8;
+ }
+ else
+ {
+ /* Must start on an odd register - r3/r4 etc. */
+ if ((greg & 1) == 0)
+ greg++;
+ if (write_pass)
+ {
+ regcache_cooked_write (regcache,
+ tdep->ppc_gp0_regnum + greg + 0,
+ val + 0);
+ regcache_cooked_write (regcache,
+ tdep->ppc_gp0_regnum + greg + 1,
+ val + 4);
+ }
+ greg += 2;
+ }
+ }
+ else if (len == 16
+ && ((TYPE_CODE (type) == TYPE_CODE_FLT
+ && (gdbarch_long_double_format (gdbarch)
+ == floatformats_ibm_long_double))
+ || (TYPE_CODE (type) == TYPE_CODE_DECFLOAT
+ && tdep->soft_float)))
+ {
+ /* Soft-float IBM long double or _Decimal128 passed in
+ four consecutive registers, or on the stack. The
+ registers are not necessarily odd/even pairs. */
+ if (greg > 7)
+ {
+ greg = 11;
+ argoffset = align_up (argoffset, 8);
+ if (write_pass)
+ write_memory (sp + argoffset, val, len);
+ argoffset += 16;
+ }
+ else
+ {
+ if (write_pass)
+ {
+ regcache_cooked_write (regcache,
+ tdep->ppc_gp0_regnum + greg + 0,
+ val + 0);
+ regcache_cooked_write (regcache,
+ tdep->ppc_gp0_regnum + greg + 1,
+ val + 4);
+ regcache_cooked_write (regcache,
+ tdep->ppc_gp0_regnum + greg + 2,
+ val + 8);
+ regcache_cooked_write (regcache,
+ tdep->ppc_gp0_regnum + greg + 3,
+ val + 12);
+ }
+ greg += 4;
+ }
+ }
+ else if (TYPE_CODE (type) == TYPE_CODE_DECFLOAT && len <= 8
+ && !tdep->soft_float)
+ {
+ /* 32-bit and 64-bit decimal floats go in f1 .. f8. They can
+ end up in memory. */
+
+ if (freg <= 8)
+ {
+ if (write_pass)
+ {
+ gdb_byte regval[MAX_REGISTER_SIZE];
+ const gdb_byte *p;
+
+ /* 32-bit decimal floats are right aligned in the
+ doubleword. */
+ if (TYPE_LENGTH (type) == 4)
+ {
+ memcpy (regval + 4, val, 4);
+ p = regval;
+ }
+ else
+ p = val;
+
+ regcache_cooked_write (regcache,
+ tdep->ppc_fp0_regnum + freg, p);
+ }
+
+ freg++;
+ }
+ else
+ {
+ argoffset = align_up (argoffset, len);
+
+ if (write_pass)
+ /* Write value in the stack's parameter save area. */
+ write_memory (sp + argoffset, val, len);
+
+ argoffset += len;
+ }
+ }
+ else if (TYPE_CODE (type) == TYPE_CODE_DECFLOAT && len == 16
+ && !tdep->soft_float)
+ {
+ /* 128-bit decimal floats go in f2 .. f7, always in even/odd
+ pairs. They can end up in memory, using two doublewords. */
+
+ if (freg <= 6)
+ {
+ /* Make sure freg is even. */
+ freg += freg & 1;
+
+ if (write_pass)
+ {
+ regcache_cooked_write (regcache,
+ tdep->ppc_fp0_regnum + freg, val);
+ regcache_cooked_write (regcache,
+ tdep->ppc_fp0_regnum + freg + 1, val + 8);
+ }
+ }
+ else
+ {
+ argoffset = align_up (argoffset, 8);
+
+ if (write_pass)
+ write_memory (sp + argoffset, val, 16);
+
+ argoffset += 16;
+ }
+
+ /* If a 128-bit decimal float goes to the stack because only f7
+ and f8 are free (thus there's no even/odd register pair
+ available), these registers should be marked as occupied.
+ Hence we increase freg even when writing to memory. */
+ freg += 2;
+ }
+ else if (len < 16
+ && TYPE_CODE (type) == TYPE_CODE_ARRAY
+ && TYPE_VECTOR (type)
+ && opencl_abi)
+ {
+ /* OpenCL vectors shorter than 16 bytes are passed as if
+ a series of independent scalars. */
+ struct type *eltype = check_typedef (TYPE_TARGET_TYPE (type));
+ int i, nelt = TYPE_LENGTH (type) / TYPE_LENGTH (eltype);
+
+ for (i = 0; i < nelt; i++)
+ {
+ const gdb_byte *elval = val + i * TYPE_LENGTH (eltype);
+
+ if (TYPE_CODE (eltype) == TYPE_CODE_FLT && !tdep->soft_float)
+ {
+ if (freg <= 8)
+ {
+ if (write_pass)
+ {
+ int regnum = tdep->ppc_fp0_regnum + freg;
+ gdb_byte regval[MAX_REGISTER_SIZE];
+ struct type *regtype
+ = register_type (gdbarch, regnum);
+ convert_typed_floating (elval, eltype,
+ regval, regtype);
+ regcache_cooked_write (regcache, regnum, regval);
+ }
+ freg++;
+ }
+ else
+ {
+ argoffset = align_up (argoffset, len);
+ if (write_pass)
+ write_memory (sp + argoffset, val, len);
+ argoffset += len;
+ }
+ }
+ else if (TYPE_LENGTH (eltype) == 8)
+ {
+ if (greg > 9)
+ {
+ /* Just in case GREG was 10. */
+ greg = 11;
+ argoffset = align_up (argoffset, 8);
+ if (write_pass)
+ write_memory (sp + argoffset, elval,
+ TYPE_LENGTH (eltype));
+ argoffset += 8;
+ }
+ else
+ {
+ /* Must start on an odd register - r3/r4 etc. */
+ if ((greg & 1) == 0)
+ greg++;
+ if (write_pass)
+ {
+ int regnum = tdep->ppc_gp0_regnum + greg;
+ regcache_cooked_write (regcache,
+ regnum + 0, elval + 0);
+ regcache_cooked_write (regcache,
+ regnum + 1, elval + 4);
+ }
+ greg += 2;
+ }
+ }
+ else
+ {
+ gdb_byte word[MAX_REGISTER_SIZE];
+ store_unsigned_integer (word, tdep->wordsize, byte_order,
+ unpack_long (eltype, elval));
+
+ if (greg <= 10)
+ {
+ if (write_pass)
+ regcache_cooked_write (regcache,
+ tdep->ppc_gp0_regnum + greg,
+ word);
+ greg++;
+ }
+ else
+ {
+ argoffset = align_up (argoffset, tdep->wordsize);
+ if (write_pass)
+ write_memory (sp + argoffset, word, tdep->wordsize);
+ argoffset += tdep->wordsize;
+ }
+ }
+ }
+ }
+ else if (len >= 16
+ && TYPE_CODE (type) == TYPE_CODE_ARRAY
+ && TYPE_VECTOR (type)
+ && opencl_abi)
+ {
+ /* OpenCL vectors 16 bytes or longer are passed as if
+ a series of AltiVec vectors. */
+ int i;
+
+ for (i = 0; i < len / 16; i++)
+ {
+ const gdb_byte *elval = val + i * 16;
+
+ if (vreg <= 13)
+ {
+ if (write_pass)
+ regcache_cooked_write (regcache,
+ tdep->ppc_vr0_regnum + vreg,
+ elval);
+ vreg++;
+ }
+ else
+ {
+ argoffset = align_up (argoffset, 16);
+ if (write_pass)
+ write_memory (sp + argoffset, elval, 16);
+ argoffset += 16;
+ }
+ }
+ }
+ else if (len == 16
+ && TYPE_CODE (type) == TYPE_CODE_ARRAY
+ && TYPE_VECTOR (type)
+ && tdep->vector_abi == POWERPC_VEC_ALTIVEC)
+ {
+ /* Vector parameter passed in an Altivec register, or
+ when that runs out, 16 byte aligned stack location. */
+ if (vreg <= 13)
+ {
+ if (write_pass)
+ regcache_cooked_write (regcache,
+ tdep->ppc_vr0_regnum + vreg, val);
+ vreg++;
+ }
+ else
+ {
+ argoffset = align_up (argoffset, 16);
+ if (write_pass)
+ write_memory (sp + argoffset, val, 16);
+ argoffset += 16;
+ }
+ }
+ else if (len == 8
+ && TYPE_CODE (type) == TYPE_CODE_ARRAY
+ && TYPE_VECTOR (type)
+ && tdep->vector_abi == POWERPC_VEC_SPE)
+ {
+ /* Vector parameter passed in an e500 register, or when
+ that runs out, 8 byte aligned stack location. Note
+ that since e500 vector and general purpose registers
+ both map onto the same underlying register set, a
+ "greg" and not a "vreg" is consumed here. A cooked
+ write stores the value in the correct locations
+ within the raw register cache. */
+ if (greg <= 10)
+ {
+ if (write_pass)
+ regcache_cooked_write (regcache,
+ tdep->ppc_ev0_regnum + greg, val);
+ greg++;
+ }
+ else
+ {
+ argoffset = align_up (argoffset, 8);
+ if (write_pass)
+ write_memory (sp + argoffset, val, 8);
+ argoffset += 8;
+ }
+ }