+
+ /* Not all PPC and RS6000 variants will have the registers
+ represented below. A -1 is used to indicate that the register
+ is not present in this variant. */
+
+ /* Floating-point registers. */
+ int ppc_fp0_regnum; /* Floating-point register 0. */
+ int ppc_fpscr_regnum; /* fp status and condition register. */
+
+ /* Multiplier-Quotient Register (older POWER architectures only). */
+ int ppc_mq_regnum;
+
+ /* POWER7 VSX registers. */
+ int ppc_vsr0_regnum; /* First VSX register. */
+ int ppc_vsr0_upper_regnum; /* First right most dword vsx register. */
+ int ppc_efpr0_regnum; /* First Extended FP register. */
+
+ /* Altivec registers. */
+ int ppc_vr0_regnum; /* First AltiVec register. */
+ int ppc_vrsave_regnum; /* Last AltiVec register. */
+
+ /* Altivec pseudo-register vX aliases for the raw vrX
+ registers. */
+ int ppc_v0_alias_regnum;
+
+ /* SPE registers. */
+ int ppc_ev0_upper_regnum; /* First GPR upper half register. */
+ int ppc_ev0_regnum; /* First ev register. */
+ int ppc_acc_regnum; /* SPE 'acc' register. */
+ int ppc_spefscr_regnum; /* SPE 'spefscr' register. */
+
+ /* Program Priority Register. */
+ int ppc_ppr_regnum;
+
+ /* Data Stream Control Register. */
+ int ppc_dscr_regnum;
+
+ /* Target Address Register. */
+ int ppc_tar_regnum;
+
+ /* Decimal 128 registers. */
+ int ppc_dl0_regnum; /* First Decimal128 argument register pair. */
+
+ int have_ebb;
+
+ /* PMU registers. */
+ int ppc_mmcr0_regnum;
+ int ppc_mmcr2_regnum;
+ int ppc_siar_regnum;
+ int ppc_sdar_regnum;
+ int ppc_sier_regnum;
+
+ /* Hardware Transactional Memory registers. */
+ int have_htm_spr;
+ int have_htm_core;
+ int have_htm_fpu;
+ int have_htm_altivec;
+ int have_htm_vsx;
+ int ppc_cppr_regnum;
+ int ppc_cdscr_regnum;
+ int ppc_ctar_regnum;
+
+ /* HTM pseudo registers. */
+ int ppc_cdl0_regnum;
+ int ppc_cvsr0_regnum;
+ int ppc_cefpr0_regnum;
+
+ /* Offset to ABI specific location where link register is saved. */
+ int lr_frame_offset;
+
+ /* An array of integers, such that sim_regno[I] is the simulator
+ register number for GDB register number I, or -1 if the
+ simulator does not implement that register. */
+ int *sim_regno;
+
+ /* ISA-specific types. */
+ struct type *ppc_builtin_type_vec64;
+ struct type *ppc_builtin_type_vec128;
+
+ int (*ppc_syscall_record) (struct regcache *regcache);
+};
+
+
+/* Constants for register set sizes. */
+enum
+ {
+ ppc_num_gprs = 32, /* 32 general-purpose registers. */
+ ppc_num_fprs = 32, /* 32 floating-point registers. */
+ ppc_num_srs = 16, /* 16 segment registers. */
+ ppc_num_vrs = 32, /* 32 Altivec vector registers. */
+ ppc_num_vshrs = 32, /* 32 doublewords (dword 1 of vs0~vs31). */
+ ppc_num_vsrs = 64, /* 64 VSX vector registers. */
+ ppc_num_efprs = 32 /* 32 Extended FP registers. */
+ };
+
+
+/* Register number constants. These are GDB internal register
+ numbers; they are not used for the simulator or remote targets.
+ Extra SPRs (those other than MQ, CTR, LR, XER, SPEFSCR) are given
+ numbers above PPC_NUM_REGS. So are segment registers and other
+ target-defined registers. */
+enum {
+ PPC_R0_REGNUM = 0,
+ PPC_F0_REGNUM = 32,
+ PPC_PC_REGNUM = 64,
+ PPC_MSR_REGNUM = 65,
+ PPC_CR_REGNUM = 66,
+ PPC_LR_REGNUM = 67,
+ PPC_CTR_REGNUM = 68,
+ PPC_XER_REGNUM = 69,
+ PPC_FPSCR_REGNUM = 70,
+ PPC_MQ_REGNUM = 71,
+ PPC_SPE_UPPER_GP0_REGNUM = 72,
+ PPC_SPE_ACC_REGNUM = 104,
+ PPC_SPE_FSCR_REGNUM = 105,
+ PPC_VR0_REGNUM = 106,
+ PPC_VSCR_REGNUM = 138,
+ PPC_VRSAVE_REGNUM = 139,
+ PPC_VSR0_UPPER_REGNUM = 140,
+ PPC_VSR31_UPPER_REGNUM = 171,
+ PPC_PPR_REGNUM = 172,
+ PPC_DSCR_REGNUM = 173,
+ PPC_TAR_REGNUM = 174,
+
+ /* EBB registers. */
+ PPC_BESCR_REGNUM = 175,
+ PPC_EBBHR_REGNUM = 176,
+ PPC_EBBRR_REGNUM = 177,
+
+ /* PMU registers. */
+ PPC_MMCR0_REGNUM = 178,
+ PPC_MMCR2_REGNUM = 179,
+ PPC_SIAR_REGNUM = 180,
+ PPC_SDAR_REGNUM = 181,
+ PPC_SIER_REGNUM = 182,
+
+ /* Hardware transactional memory registers. */
+ PPC_TFHAR_REGNUM = 183,
+ PPC_TEXASR_REGNUM = 184,
+ PPC_TFIAR_REGNUM = 185,
+
+ PPC_CR0_REGNUM = 186,
+ PPC_CCR_REGNUM = 218,
+ PPC_CXER_REGNUM = 219,
+ PPC_CLR_REGNUM = 220,
+ PPC_CCTR_REGNUM = 221,
+
+ PPC_CF0_REGNUM = 222,
+ PPC_CFPSCR_REGNUM = 254,
+
+ PPC_CVR0_REGNUM = 255,
+ PPC_CVSCR_REGNUM = 287,
+ PPC_CVRSAVE_REGNUM = 288,
+
+ PPC_CVSR0_UPPER_REGNUM = 289,
+
+ PPC_CPPR_REGNUM = 321,
+ PPC_CDSCR_REGNUM = 322,
+ PPC_CTAR_REGNUM = 323,
+ PPC_NUM_REGS
+};
+
+/* Big enough to hold the size of the largest register in bytes. */
+#define PPC_MAX_REGISTER_SIZE 64
+
+#define PPC_IS_EBB_REGNUM(i) \
+ ((i) >= PPC_BESCR_REGNUM && (i) <= PPC_EBBRR_REGNUM)
+
+#define PPC_IS_PMU_REGNUM(i) \
+ ((i) >= PPC_MMCR0_REGNUM && (i) <= PPC_SIER_REGNUM)
+
+#define PPC_IS_TMSPR_REGNUM(i) \
+ ((i) >= PPC_TFHAR_REGNUM && (i) <= PPC_TFIAR_REGNUM)
+
+#define PPC_IS_CKPTGP_REGNUM(i) \
+ ((i) >= PPC_CR0_REGNUM && (i) <= PPC_CCTR_REGNUM)
+
+#define PPC_IS_CKPTFP_REGNUM(i) \
+ ((i) >= PPC_CF0_REGNUM && (i) <= PPC_CFPSCR_REGNUM)
+
+#define PPC_IS_CKPTVMX_REGNUM(i) \
+ ((i) >= PPC_CVR0_REGNUM && (i) <= PPC_CVRSAVE_REGNUM)
+
+#define PPC_IS_CKPTVSX_REGNUM(i) \
+ ((i) >= PPC_CVSR0_UPPER_REGNUM && (i) < (PPC_CVSR0_UPPER_REGNUM + 32))
+
+/* An instruction to match. */
+
+struct ppc_insn_pattern
+{
+ unsigned int mask; /* mask the insn with this... */
+ unsigned int data; /* ...and see if it matches this. */
+ int optional; /* If non-zero, this insn may be absent. */