+/* Register number constants. These are GDB internal register
+ numbers; they are not used for the simulator or remote targets.
+ Extra SPRs (those other than MQ, CTR, LR, XER, SPEFSCR) are given
+ numbers above PPC_NUM_REGS. So are segment registers and other
+ target-defined registers. */
+enum {
+ PPC_R0_REGNUM = 0,
+ PPC_F0_REGNUM = 32,
+ PPC_PC_REGNUM = 64,
+ PPC_MSR_REGNUM = 65,
+ PPC_CR_REGNUM = 66,
+ PPC_LR_REGNUM = 67,
+ PPC_CTR_REGNUM = 68,
+ PPC_XER_REGNUM = 69,
+ PPC_FPSCR_REGNUM = 70,
+ PPC_MQ_REGNUM = 71,
+ PPC_SPE_UPPER_GP0_REGNUM = 72,
+ PPC_SPE_ACC_REGNUM = 104,
+ PPC_SPE_FSCR_REGNUM = 105,
+ PPC_VR0_REGNUM = 106,
+ PPC_VSCR_REGNUM = 138,
+ PPC_VRSAVE_REGNUM = 139,
+ PPC_VSR0_UPPER_REGNUM = 140,
+ PPC_VSR31_UPPER_REGNUM = 171,
+ PPC_PPR_REGNUM = 172,
+ PPC_DSCR_REGNUM = 173,
+ PPC_TAR_REGNUM = 174,
+
+ /* EBB registers. */
+ PPC_BESCR_REGNUM = 175,
+ PPC_EBBHR_REGNUM = 176,
+ PPC_EBBRR_REGNUM = 177,
+
+ /* PMU registers. */
+ PPC_MMCR0_REGNUM = 178,
+ PPC_MMCR2_REGNUM = 179,
+ PPC_SIAR_REGNUM = 180,
+ PPC_SDAR_REGNUM = 181,
+ PPC_SIER_REGNUM = 182,
+
+ /* Hardware transactional memory registers. */
+ PPC_TFHAR_REGNUM = 183,
+ PPC_TEXASR_REGNUM = 184,
+ PPC_TFIAR_REGNUM = 185,
+
+ PPC_CR0_REGNUM = 186,
+ PPC_CCR_REGNUM = 218,
+ PPC_CXER_REGNUM = 219,
+ PPC_CLR_REGNUM = 220,
+ PPC_CCTR_REGNUM = 221,
+
+ PPC_CF0_REGNUM = 222,
+ PPC_CFPSCR_REGNUM = 254,
+
+ PPC_CVR0_REGNUM = 255,
+ PPC_CVSCR_REGNUM = 287,
+ PPC_CVRSAVE_REGNUM = 288,
+
+ PPC_CVSR0_UPPER_REGNUM = 289,
+
+ PPC_CPPR_REGNUM = 321,
+ PPC_CDSCR_REGNUM = 322,
+ PPC_CTAR_REGNUM = 323,
+ PPC_NUM_REGS
+};