+ /* ABI version. */
+ enum { ABI_LINUX_S390, ABI_LINUX_ZSERIES } abi;
+
+ /* Core file register sets. */
+ const struct regset *gregset;
+ int sizeof_gregset;
+
+ const struct regset *fpregset;
+ int sizeof_fpregset;
+};
+
+
+/* Register information. */
+
+struct s390_register_info
+{
+ char *name;
+ struct type **type;
+};
+
+static struct s390_register_info s390_register_info[S390_NUM_TOTAL_REGS] =
+{
+ /* Program Status Word. */
+ { "pswm", &builtin_type_long },
+ { "pswa", &builtin_type_long },
+
+ /* General Purpose Registers. */
+ { "r0", &builtin_type_long },
+ { "r1", &builtin_type_long },
+ { "r2", &builtin_type_long },
+ { "r3", &builtin_type_long },
+ { "r4", &builtin_type_long },
+ { "r5", &builtin_type_long },
+ { "r6", &builtin_type_long },
+ { "r7", &builtin_type_long },
+ { "r8", &builtin_type_long },
+ { "r9", &builtin_type_long },
+ { "r10", &builtin_type_long },
+ { "r11", &builtin_type_long },
+ { "r12", &builtin_type_long },
+ { "r13", &builtin_type_long },
+ { "r14", &builtin_type_long },
+ { "r15", &builtin_type_long },
+
+ /* Access Registers. */
+ { "acr0", &builtin_type_int },
+ { "acr1", &builtin_type_int },
+ { "acr2", &builtin_type_int },
+ { "acr3", &builtin_type_int },
+ { "acr4", &builtin_type_int },
+ { "acr5", &builtin_type_int },
+ { "acr6", &builtin_type_int },
+ { "acr7", &builtin_type_int },
+ { "acr8", &builtin_type_int },
+ { "acr9", &builtin_type_int },
+ { "acr10", &builtin_type_int },
+ { "acr11", &builtin_type_int },
+ { "acr12", &builtin_type_int },
+ { "acr13", &builtin_type_int },
+ { "acr14", &builtin_type_int },
+ { "acr15", &builtin_type_int },
+
+ /* Floating Point Control Word. */
+ { "fpc", &builtin_type_int },
+
+ /* Floating Point Registers. */
+ { "f0", &builtin_type_double },
+ { "f1", &builtin_type_double },
+ { "f2", &builtin_type_double },
+ { "f3", &builtin_type_double },
+ { "f4", &builtin_type_double },
+ { "f5", &builtin_type_double },
+ { "f6", &builtin_type_double },
+ { "f7", &builtin_type_double },
+ { "f8", &builtin_type_double },
+ { "f9", &builtin_type_double },
+ { "f10", &builtin_type_double },
+ { "f11", &builtin_type_double },
+ { "f12", &builtin_type_double },
+ { "f13", &builtin_type_double },
+ { "f14", &builtin_type_double },
+ { "f15", &builtin_type_double },
+
+ /* Pseudo registers. */
+ { "pc", &builtin_type_void_func_ptr },
+ { "cc", &builtin_type_int },
+};
+
+/* Return the name of register REGNUM. */
+static const char *
+s390_register_name (int regnum)
+{
+ gdb_assert (regnum >= 0 && regnum < S390_NUM_TOTAL_REGS);
+ return s390_register_info[regnum].name;
+}
+
+/* Return the GDB type object for the "standard" data type of data in
+ register REGNUM. */
+static struct type *
+s390_register_type (struct gdbarch *gdbarch, int regnum)
+{
+ gdb_assert (regnum >= 0 && regnum < S390_NUM_TOTAL_REGS);
+ return *s390_register_info[regnum].type;
+}
+
+/* DWARF Register Mapping. */
+
+static int s390_dwarf_regmap[] =
+{
+ /* General Purpose Registers. */
+ S390_R0_REGNUM, S390_R1_REGNUM, S390_R2_REGNUM, S390_R3_REGNUM,
+ S390_R4_REGNUM, S390_R5_REGNUM, S390_R6_REGNUM, S390_R7_REGNUM,
+ S390_R8_REGNUM, S390_R9_REGNUM, S390_R10_REGNUM, S390_R11_REGNUM,
+ S390_R12_REGNUM, S390_R13_REGNUM, S390_R14_REGNUM, S390_R15_REGNUM,
+
+ /* Floating Point Registers. */
+ S390_F0_REGNUM, S390_F2_REGNUM, S390_F4_REGNUM, S390_F6_REGNUM,
+ S390_F1_REGNUM, S390_F3_REGNUM, S390_F5_REGNUM, S390_F7_REGNUM,
+ S390_F8_REGNUM, S390_F10_REGNUM, S390_F12_REGNUM, S390_F14_REGNUM,
+ S390_F9_REGNUM, S390_F11_REGNUM, S390_F13_REGNUM, S390_F15_REGNUM,
+
+ /* Control Registers (not mapped). */
+ -1, -1, -1, -1, -1, -1, -1, -1,
+ -1, -1, -1, -1, -1, -1, -1, -1,
+
+ /* Access Registers. */
+ S390_A0_REGNUM, S390_A1_REGNUM, S390_A2_REGNUM, S390_A3_REGNUM,
+ S390_A4_REGNUM, S390_A5_REGNUM, S390_A6_REGNUM, S390_A7_REGNUM,
+ S390_A8_REGNUM, S390_A9_REGNUM, S390_A10_REGNUM, S390_A11_REGNUM,
+ S390_A12_REGNUM, S390_A13_REGNUM, S390_A14_REGNUM, S390_A15_REGNUM,
+
+ /* Program Status Word. */
+ S390_PSWM_REGNUM,
+ S390_PSWA_REGNUM
+};
+
+/* Convert DWARF register number REG to the appropriate register
+ number used by GDB. */
+static int
+s390_dwarf_reg_to_regnum (int reg)
+{
+ int regnum = -1;
+
+ if (reg >= 0 && reg < ARRAY_SIZE (s390_dwarf_regmap))
+ regnum = s390_dwarf_regmap[reg];
+
+ if (regnum == -1)
+ warning (_("Unmapped DWARF Register #%d encountered."), reg);
+
+ return regnum;
+}
+
+/* Pseudo registers - PC and condition code. */
+
+static void
+s390_pseudo_register_read (struct gdbarch *gdbarch, struct regcache *regcache,
+ int regnum, void *buf)
+{
+ ULONGEST val;
+
+ switch (regnum)
+ {
+ case S390_PC_REGNUM:
+ regcache_raw_read_unsigned (regcache, S390_PSWA_REGNUM, &val);
+ store_unsigned_integer (buf, 4, val & 0x7fffffff);
+ break;
+
+ case S390_CC_REGNUM:
+ regcache_raw_read_unsigned (regcache, S390_PSWM_REGNUM, &val);
+ store_unsigned_integer (buf, 4, (val >> 12) & 3);
+ break;
+
+ default:
+ internal_error (__FILE__, __LINE__, _("invalid regnum"));
+ }
+}
+
+static void
+s390_pseudo_register_write (struct gdbarch *gdbarch, struct regcache *regcache,
+ int regnum, const void *buf)
+{
+ ULONGEST val, psw;
+
+ switch (regnum)
+ {
+ case S390_PC_REGNUM:
+ val = extract_unsigned_integer (buf, 4);
+ regcache_raw_read_unsigned (regcache, S390_PSWA_REGNUM, &psw);
+ psw = (psw & 0x80000000) | (val & 0x7fffffff);
+ regcache_raw_write_unsigned (regcache, S390_PSWA_REGNUM, psw);
+ break;
+
+ case S390_CC_REGNUM:
+ val = extract_unsigned_integer (buf, 4);
+ regcache_raw_read_unsigned (regcache, S390_PSWM_REGNUM, &psw);
+ psw = (psw & ~((ULONGEST)3 << 12)) | ((val & 3) << 12);
+ regcache_raw_write_unsigned (regcache, S390_PSWM_REGNUM, psw);
+ break;
+
+ default:
+ internal_error (__FILE__, __LINE__, _("invalid regnum"));
+ }
+}
+
+static void
+s390x_pseudo_register_read (struct gdbarch *gdbarch, struct regcache *regcache,
+ int regnum, void *buf)
+{
+ ULONGEST val;
+
+ switch (regnum)
+ {
+ case S390_PC_REGNUM:
+ regcache_raw_read (regcache, S390_PSWA_REGNUM, buf);
+ break;
+
+ case S390_CC_REGNUM:
+ regcache_raw_read_unsigned (regcache, S390_PSWM_REGNUM, &val);
+ store_unsigned_integer (buf, 4, (val >> 44) & 3);
+ break;
+
+ default:
+ internal_error (__FILE__, __LINE__, _("invalid regnum"));
+ }
+}
+
+static void
+s390x_pseudo_register_write (struct gdbarch *gdbarch, struct regcache *regcache,
+ int regnum, const void *buf)
+{
+ ULONGEST val, psw;
+
+ switch (regnum)
+ {
+ case S390_PC_REGNUM:
+ regcache_raw_write (regcache, S390_PSWA_REGNUM, buf);
+ break;
+
+ case S390_CC_REGNUM:
+ val = extract_unsigned_integer (buf, 4);
+ regcache_raw_read_unsigned (regcache, S390_PSWM_REGNUM, &psw);
+ psw = (psw & ~((ULONGEST)3 << 44)) | ((val & 3) << 44);
+ regcache_raw_write_unsigned (regcache, S390_PSWM_REGNUM, psw);
+ break;
+
+ default:
+ internal_error (__FILE__, __LINE__, _("invalid regnum"));
+ }
+}
+
+/* 'float' values are stored in the upper half of floating-point
+ registers, even though we are otherwise a big-endian platform. */
+
+static int
+s390_convert_register_p (int regno, struct type *type)
+{
+ return (regno >= S390_F0_REGNUM && regno <= S390_F15_REGNUM)
+ && TYPE_LENGTH (type) < 8;
+}
+
+static void
+s390_register_to_value (struct frame_info *frame, int regnum,
+ struct type *valtype, void *out)
+{
+ char in[8];
+ int len = TYPE_LENGTH (valtype);
+ gdb_assert (len < 8);
+
+ get_frame_register (frame, regnum, in);
+ memcpy (out, in, len);
+}
+
+static void
+s390_value_to_register (struct frame_info *frame, int regnum,
+ struct type *valtype, const void *in)
+{
+ char out[8];
+ int len = TYPE_LENGTH (valtype);
+ gdb_assert (len < 8);
+
+ memset (out, 0, 8);
+ memcpy (out, in, len);
+ put_frame_register (frame, regnum, out);
+}
+
+/* Register groups. */
+
+static int
+s390_register_reggroup_p (struct gdbarch *gdbarch, int regnum,
+ struct reggroup *group)
+{
+ struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
+
+ /* Registers displayed via 'info regs'. */
+ if (group == general_reggroup)
+ return (regnum >= S390_R0_REGNUM && regnum <= S390_R15_REGNUM)
+ || regnum == S390_PC_REGNUM
+ || regnum == S390_CC_REGNUM;
+
+ /* Registers displayed via 'info float'. */
+ if (group == float_reggroup)
+ return (regnum >= S390_F0_REGNUM && regnum <= S390_F15_REGNUM)
+ || regnum == S390_FPC_REGNUM;
+
+ /* Registers that need to be saved/restored in order to
+ push or pop frames. */
+ if (group == save_reggroup || group == restore_reggroup)
+ return regnum != S390_PSWM_REGNUM && regnum != S390_PSWA_REGNUM;
+
+ return default_register_reggroup_p (gdbarch, regnum, group);
+}
+
+
+/* Core file register sets. */
+
+int s390_regmap_gregset[S390_NUM_REGS] =
+{
+ /* Program Status Word. */
+ 0x00, 0x04,
+ /* General Purpose Registers. */
+ 0x08, 0x0c, 0x10, 0x14,
+ 0x18, 0x1c, 0x20, 0x24,
+ 0x28, 0x2c, 0x30, 0x34,
+ 0x38, 0x3c, 0x40, 0x44,
+ /* Access Registers. */
+ 0x48, 0x4c, 0x50, 0x54,
+ 0x58, 0x5c, 0x60, 0x64,
+ 0x68, 0x6c, 0x70, 0x74,
+ 0x78, 0x7c, 0x80, 0x84,
+ /* Floating Point Control Word. */
+ -1,
+ /* Floating Point Registers. */
+ -1, -1, -1, -1, -1, -1, -1, -1,
+ -1, -1, -1, -1, -1, -1, -1, -1,
+};
+
+int s390x_regmap_gregset[S390_NUM_REGS] =
+{
+ 0x00, 0x08,
+ /* General Purpose Registers. */
+ 0x10, 0x18, 0x20, 0x28,
+ 0x30, 0x38, 0x40, 0x48,
+ 0x50, 0x58, 0x60, 0x68,
+ 0x70, 0x78, 0x80, 0x88,
+ /* Access Registers. */
+ 0x90, 0x94, 0x98, 0x9c,
+ 0xa0, 0xa4, 0xa8, 0xac,
+ 0xb0, 0xb4, 0xb8, 0xbc,
+ 0xc0, 0xc4, 0xc8, 0xcc,
+ /* Floating Point Control Word. */
+ -1,
+ /* Floating Point Registers. */
+ -1, -1, -1, -1, -1, -1, -1, -1,
+ -1, -1, -1, -1, -1, -1, -1, -1,
+};
+
+int s390_regmap_fpregset[S390_NUM_REGS] =
+{
+ /* Program Status Word. */
+ -1, -1,
+ /* General Purpose Registers. */
+ -1, -1, -1, -1, -1, -1, -1, -1,
+ -1, -1, -1, -1, -1, -1, -1, -1,
+ /* Access Registers. */
+ -1, -1, -1, -1, -1, -1, -1, -1,
+ -1, -1, -1, -1, -1, -1, -1, -1,
+ /* Floating Point Control Word. */
+ 0x00,
+ /* Floating Point Registers. */
+ 0x08, 0x10, 0x18, 0x20,
+ 0x28, 0x30, 0x38, 0x40,
+ 0x48, 0x50, 0x58, 0x60,
+ 0x68, 0x70, 0x78, 0x80,
+};
+
+/* Supply register REGNUM from the register set REGSET to register cache
+ REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */
+static void
+s390_supply_regset (const struct regset *regset, struct regcache *regcache,
+ int regnum, const void *regs, size_t len)
+{
+ const int *offset = regset->descr;
+ int i;
+
+ for (i = 0; i < S390_NUM_REGS; i++)
+ {
+ if ((regnum == i || regnum == -1) && offset[i] != -1)
+ regcache_raw_supply (regcache, i, (const char *)regs + offset[i]);
+ }
+}
+
+static const struct regset s390_gregset = {
+ s390_regmap_gregset,
+ s390_supply_regset
+};
+
+static const struct regset s390x_gregset = {
+ s390x_regmap_gregset,
+ s390_supply_regset
+};
+
+static const struct regset s390_fpregset = {
+ s390_regmap_fpregset,
+ s390_supply_regset
+};
+
+/* Return the appropriate register set for the core section identified
+ by SECT_NAME and SECT_SIZE. */
+const struct regset *
+s390_regset_from_core_section (struct gdbarch *gdbarch,
+ const char *sect_name, size_t sect_size)
+{
+ struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
+
+ if (strcmp (sect_name, ".reg") == 0 && sect_size == tdep->sizeof_gregset)
+ return tdep->gregset;
+
+ if (strcmp (sect_name, ".reg2") == 0 && sect_size == tdep->sizeof_fpregset)
+ return tdep->fpregset;
+
+ return NULL;
+}
+
+
+/* Prologue analysis. */
+
+/* When we analyze a prologue, we're really doing 'abstract
+ interpretation' or 'pseudo-evaluation': running the function's code
+ in simulation, but using conservative approximations of the values
+ it would have when it actually runs. For example, if our function
+ starts with the instruction:
+
+ ahi r1, 42 # add halfword immediate 42 to r1
+
+ we don't know exactly what value will be in r1 after executing this
+ instruction, but we do know it'll be 42 greater than its original
+ value.
+
+ If we then see an instruction like:
+
+ ahi r1, 22 # add halfword immediate 22 to r1
+
+ we still don't know what r1's value is, but again, we can say it is
+ now 64 greater than its original value.
+
+ If the next instruction were:
+
+ lr r2, r1 # set r2 to r1's value
+
+ then we can say that r2's value is now the original value of r1
+ plus 64. And so on.
+
+ Of course, this can only go so far before it gets unreasonable. If
+ we wanted to be able to say anything about the value of r1 after
+ the instruction:
+
+ xr r1, r3 # exclusive-or r1 and r3, place result in r1
+
+ then things would get pretty complex. But remember, we're just
+ doing a conservative approximation; if exclusive-or instructions
+ aren't relevant to prologues, we can just say r1's value is now
+ 'unknown'. We can ignore things that are too complex, if that loss
+ of information is acceptable for our application.
+
+ Once you've reached an instruction that you don't know how to
+ simulate, you stop. Now you examine the state of the registers and
+ stack slots you've kept track of. For example:
+
+ - To see how large your stack frame is, just check the value of sp;
+ if it's the original value of sp minus a constant, then that
+ constant is the stack frame's size. If the sp's value has been
+ marked as 'unknown', then that means the prologue has done
+ something too complex for us to track, and we don't know the
+ frame size.
+
+ - To see whether we've saved the SP in the current frame's back
+ chain slot, we just check whether the current value of the back
+ chain stack slot is the original value of the sp.
+
+ Sure, this takes some work. But prologue analyzers aren't
+ quick-and-simple pattern patching to recognize a few fixed prologue
+ forms any more; they're big, hairy functions. Along with inferior
+ function calls, prologue analysis accounts for a substantial
+ portion of the time needed to stabilize a GDB port. So I think
+ it's worthwhile to look for an approach that will be easier to
+ understand and maintain. In the approach used here:
+
+ - It's easier to see that the analyzer is correct: you just see
+ whether the analyzer properly (albiet conservatively) simulates
+ the effect of each instruction.
+
+ - It's easier to extend the analyzer: you can add support for new
+ instructions, and know that you haven't broken anything that
+ wasn't already broken before.
+
+ - It's orthogonal: to gather new information, you don't need to
+ complicate the code for each instruction. As long as your domain
+ of conservative values is already detailed enough to tell you
+ what you need, then all the existing instruction simulations are
+ already gathering the right data for you.
+
+ A 'struct prologue_value' is a conservative approximation of the
+ real value the register or stack slot will have. */
+
+struct prologue_value {
+
+ /* What sort of value is this? This determines the interpretation
+ of subsequent fields. */
+ enum {
+
+ /* We don't know anything about the value. This is also used for
+ values we could have kept track of, when doing so would have
+ been too complex and we don't want to bother. The bottom of
+ our lattice. */
+ pv_unknown,
+
+ /* A known constant. K is its value. */
+ pv_constant,
+
+ /* The value that register REG originally had *UPON ENTRY TO THE
+ FUNCTION*, plus K. If K is zero, this means, obviously, just
+ the value REG had upon entry to the function. REG is a GDB
+ register number. Before we start interpreting, we initialize
+ every register R to { pv_register, R, 0 }. */
+ pv_register,
+
+ } kind;
+
+ /* The meanings of the following fields depend on 'kind'; see the
+ comments for the specific 'kind' values. */
+ int reg;
+ CORE_ADDR k;
+};
+
+
+/* Set V to be unknown. */
+static void
+pv_set_to_unknown (struct prologue_value *v)
+{
+ v->kind = pv_unknown;
+}
+
+
+/* Set V to the constant K. */
+static void
+pv_set_to_constant (struct prologue_value *v, CORE_ADDR k)
+{
+ v->kind = pv_constant;
+ v->k = k;
+}
+
+
+/* Set V to the original value of register REG, plus K. */
+static void
+pv_set_to_register (struct prologue_value *v, int reg, CORE_ADDR k)
+{
+ v->kind = pv_register;
+ v->reg = reg;
+ v->k = k;
+}
+
+
+/* If one of *A and *B is a constant, and the other isn't, swap the
+ pointers as necessary to ensure that *B points to the constant.
+ This can reduce the number of cases we need to analyze in the
+ functions below. */
+static void
+pv_constant_last (struct prologue_value **a,
+ struct prologue_value **b)
+{
+ if ((*a)->kind == pv_constant
+ && (*b)->kind != pv_constant)
+ {
+ struct prologue_value *temp = *a;
+ *a = *b;
+ *b = temp;
+ }
+}
+
+
+/* Set SUM to the sum of A and B. SUM, A, and B may point to the same
+ 'struct prologue_value' object. */
+static void
+pv_add (struct prologue_value *sum,
+ struct prologue_value *a,
+ struct prologue_value *b)
+{
+ pv_constant_last (&a, &b);
+
+ /* We can handle adding constants to registers, and other constants. */
+ if (b->kind == pv_constant
+ && (a->kind == pv_register
+ || a->kind == pv_constant))
+ {
+ sum->kind = a->kind;
+ sum->reg = a->reg; /* not meaningful if a is pv_constant, but
+ harmless */
+ sum->k = a->k + b->k;
+ }
+
+ /* Anything else we don't know how to add. We don't have a
+ representation for, say, the sum of two registers, or a multiple
+ of a register's value (adding a register to itself). */
+ else
+ sum->kind = pv_unknown;
+}
+
+
+/* Add the constant K to V. */
+static void
+pv_add_constant (struct prologue_value *v, CORE_ADDR k)
+{
+ struct prologue_value pv_k;
+
+ /* Rather than thinking of all the cases we can and can't handle,
+ we'll just let pv_add take care of that for us. */
+ pv_set_to_constant (&pv_k, k);
+ pv_add (v, v, &pv_k);
+}
+
+
+/* Subtract B from A, and put the result in DIFF.
+
+ This isn't quite the same as negating B and adding it to A, since
+ we don't have a representation for the negation of anything but a
+ constant. For example, we can't negate { pv_register, R1, 10 },
+ but we do know that { pv_register, R1, 10 } minus { pv_register,
+ R1, 5 } is { pv_constant, <ignored>, 5 }.
+
+ This means, for example, that we can subtract two stack addresses;
+ they're both relative to the original SP. Since the frame pointer
+ is set based on the SP, its value will be the original SP plus some
+ constant (probably zero), so we can use its value just fine. */
+static void
+pv_subtract (struct prologue_value *diff,
+ struct prologue_value *a,
+ struct prologue_value *b)
+{
+ pv_constant_last (&a, &b);
+
+ /* We can subtract a constant from another constant, or from a
+ register. */
+ if (b->kind == pv_constant
+ && (a->kind == pv_register
+ || a->kind == pv_constant))
+ {
+ diff->kind = a->kind;
+ diff->reg = a->reg; /* not always meaningful, but harmless */
+ diff->k = a->k - b->k;
+ }
+
+ /* We can subtract a register from itself, yielding a constant. */
+ else if (a->kind == pv_register
+ && b->kind == pv_register
+ && a->reg == b->reg)
+ {
+ diff->kind = pv_constant;
+ diff->k = a->k - b->k;
+ }
+
+ /* We don't know how to subtract anything else. */
+ else
+ diff->kind = pv_unknown;
+}
+
+
+/* Set AND to the logical and of A and B. */
+static void
+pv_logical_and (struct prologue_value *and,
+ struct prologue_value *a,
+ struct prologue_value *b)
+{
+ pv_constant_last (&a, &b);
+
+ /* We can 'and' two constants. */
+ if (a->kind == pv_constant
+ && b->kind == pv_constant)
+ {
+ and->kind = pv_constant;
+ and->k = a->k & b->k;
+ }
+
+ /* We can 'and' anything with the constant zero. */
+ else if (b->kind == pv_constant
+ && b->k == 0)
+ {
+ and->kind = pv_constant;
+ and->k = 0;
+ }
+
+ /* We can 'and' anything with ~0. */
+ else if (b->kind == pv_constant
+ && b->k == ~ (CORE_ADDR) 0)
+ *and = *a;
+
+ /* We can 'and' a register with itself. */
+ else if (a->kind == pv_register
+ && b->kind == pv_register
+ && a->reg == b->reg
+ && a->k == b->k)
+ *and = *a;
+
+ /* Otherwise, we don't know. */