+/* On the Sun 4 under SunOS, the compile will leave a fake insn which
+ encodes the structure size being returned. If we detect such
+ a fake insn, step past it. */
+
+CORE_ADDR
+sparc_pc_adjust (pc)
+ CORE_ADDR pc;
+{
+ unsigned long insn;
+ char buf[4];
+ int err;
+
+ err = target_read_memory (pc + 8, buf, 4);
+ insn = extract_unsigned_integer (buf, 4);
+ if ((err == 0) && (insn & 0xffc00000) == 0)
+ return pc + 12;
+ else
+ return pc + 8;
+}
+
+/* If pc is in a shared library trampoline, return its target.
+ The SunOs 4.x linker rewrites the jump table entries for PIC
+ compiled modules in the main executable to bypass the dynamic linker
+ with jumps of the form
+ sethi %hi(addr),%g1
+ jmp %g1+%lo(addr)
+ and removes the corresponding jump table relocation entry in the
+ dynamic relocations.
+ find_solib_trampoline_target relies on the presence of the jump
+ table relocation entry, so we have to detect these jump instructions
+ by hand. */
+
+CORE_ADDR
+sunos4_skip_trampoline_code (pc)
+ CORE_ADDR pc;
+{
+ unsigned long insn1;
+ char buf[4];
+ int err;
+
+ err = target_read_memory (pc, buf, 4);
+ insn1 = extract_unsigned_integer (buf, 4);
+ if (err == 0 && (insn1 & 0xffc00000) == 0x03000000)
+ {
+ unsigned long insn2;
+
+ err = target_read_memory (pc + 4, buf, 4);
+ insn2 = extract_unsigned_integer (buf, 4);
+ if (err == 0 && (insn2 & 0xffffe000) == 0x81c06000)
+ {
+ CORE_ADDR target_pc = (insn1 & 0x3fffff) << 10;
+ int delta = insn2 & 0x1fff;
+
+ /* Sign extend the displacement. */
+ if (delta & 0x1000)
+ delta |= ~0x1fff;
+ return target_pc + delta;
+ }
+ }
+ return find_solib_trampoline_target (pc);
+}
+\f
+#ifdef USE_PROC_FS /* Target dependent support for /proc */
+/* *INDENT-OFF* */
+/* The /proc interface divides the target machine's register set up into
+ two different sets, the general register set (gregset) and the floating
+ point register set (fpregset). For each set, there is an ioctl to get
+ the current register set and another ioctl to set the current values.
+
+ The actual structure passed through the ioctl interface is, of course,
+ naturally machine dependent, and is different for each set of registers.
+ For the sparc for example, the general register set is typically defined
+ by:
+
+ typedef int gregset_t[38];
+
+ #define R_G0 0
+ ...
+ #define R_TBR 37
+
+ and the floating point set by:
+
+ typedef struct prfpregset {
+ union {
+ u_long pr_regs[32];
+ double pr_dregs[16];
+ } pr_fr;
+ void * pr_filler;
+ u_long pr_fsr;
+ u_char pr_qcnt;
+ u_char pr_q_entrysize;
+ u_char pr_en;
+ u_long pr_q[64];
+ } prfpregset_t;
+
+ These routines provide the packing and unpacking of gregset_t and
+ fpregset_t formatted data.
+
+ */
+/* *INDENT-ON* */
+
+
+
+/* Given a pointer to a general register set in /proc format (gregset_t *),
+ unpack the register contents and supply them as gdb's idea of the current
+ register values. */
+
+void
+supply_gregset (gregsetp)
+ prgregset_t *gregsetp;
+{
+ register int regi;
+ register prgreg_t *regp = (prgreg_t *) gregsetp;
+ static char zerobuf[MAX_REGISTER_RAW_SIZE] =
+ {0};
+
+ /* GDB register numbers for Gn, On, Ln, In all match /proc reg numbers. */
+ for (regi = G0_REGNUM; regi <= I7_REGNUM; regi++)
+ {
+ supply_register (regi, (char *) (regp + regi));
+ }
+
+ /* These require a bit more care. */
+ supply_register (PS_REGNUM, (char *) (regp + R_PS));
+ supply_register (PC_REGNUM, (char *) (regp + R_PC));
+ supply_register (NPC_REGNUM, (char *) (regp + R_nPC));
+ supply_register (Y_REGNUM, (char *) (regp + R_Y));
+
+ /* Fill inaccessible registers with zero. */
+ supply_register (WIM_REGNUM, zerobuf);
+ supply_register (TBR_REGNUM, zerobuf);
+ supply_register (CPS_REGNUM, zerobuf);
+}
+
+void
+fill_gregset (gregsetp, regno)
+ prgregset_t *gregsetp;
+ int regno;
+{
+ int regi;
+ register prgreg_t *regp = (prgreg_t *) gregsetp;
+
+ for (regi = 0; regi <= R_I7; regi++)
+ {
+ if ((regno == -1) || (regno == regi))
+ {
+ *(regp + regi) = *(int *) ®isters[REGISTER_BYTE (regi)];
+ }
+ }
+ if ((regno == -1) || (regno == PS_REGNUM))
+ {
+ *(regp + R_PS) = *(int *) ®isters[REGISTER_BYTE (PS_REGNUM)];
+ }
+ if ((regno == -1) || (regno == PC_REGNUM))
+ {
+ *(regp + R_PC) = *(int *) ®isters[REGISTER_BYTE (PC_REGNUM)];
+ }
+ if ((regno == -1) || (regno == NPC_REGNUM))
+ {
+ *(regp + R_nPC) = *(int *) ®isters[REGISTER_BYTE (NPC_REGNUM)];
+ }
+ if ((regno == -1) || (regno == Y_REGNUM))
+ {
+ *(regp + R_Y) = *(int *) ®isters[REGISTER_BYTE (Y_REGNUM)];
+ }
+}
+
+#if defined (FP0_REGNUM)
+
+/* Given a pointer to a floating point register set in /proc format
+ (fpregset_t *), unpack the register contents and supply them as gdb's
+ idea of the current floating point register values. */
+
+void
+supply_fpregset (fpregsetp)
+ prfpregset_t *fpregsetp;
+{
+ register int regi;
+ char *from;
+
+ for (regi = FP0_REGNUM; regi < FP_MAX_REGNUM; regi++)
+ {
+ from = (char *) &fpregsetp->pr_fr.pr_regs[regi - FP0_REGNUM];
+ supply_register (regi, from);
+ }
+ supply_register (FPS_REGNUM, (char *) &(fpregsetp->pr_fsr));
+}
+
+/* Given a pointer to a floating point register set in /proc format
+ (fpregset_t *), update the register specified by REGNO from gdb's idea
+ of the current floating point register set. If REGNO is -1, update
+ them all. */
+/* ??? This will probably need some changes for sparc64. */
+
+void
+fill_fpregset (fpregsetp, regno)
+ prfpregset_t *fpregsetp;
+ int regno;
+{
+ int regi;
+ char *to;
+ char *from;
+
+ for (regi = FP0_REGNUM; regi < FP_MAX_REGNUM; regi++)
+ {
+ if ((regno == -1) || (regno == regi))
+ {
+ from = (char *) ®isters[REGISTER_BYTE (regi)];
+ to = (char *) &fpregsetp->pr_fr.pr_regs[regi - FP0_REGNUM];
+ memcpy (to, from, REGISTER_RAW_SIZE (regi));
+ }
+ }
+ if ((regno == -1) || (regno == FPS_REGNUM))
+ {
+ fpregsetp->pr_fsr = *(int *) ®isters[REGISTER_BYTE (FPS_REGNUM)];
+ }
+}
+
+#endif /* defined (FP0_REGNUM) */
+
+#endif /* USE_PROC_FS */
+
+
+#ifdef GET_LONGJMP_TARGET
+
+/* Figure out where the longjmp will land. We expect that we have just entered
+ longjmp and haven't yet setup the stack frame, so the args are still in the
+ output regs. %o0 (O0_REGNUM) points at the jmp_buf structure from which we
+ extract the pc (JB_PC) that we will land at. The pc is copied into ADDR.
+ This routine returns true on success */
+
+int
+get_longjmp_target (pc)
+ CORE_ADDR *pc;
+{
+ CORE_ADDR jb_addr;
+#define LONGJMP_TARGET_SIZE 4
+ char buf[LONGJMP_TARGET_SIZE];
+
+ jb_addr = read_register (O0_REGNUM);
+
+ if (target_read_memory (jb_addr + JB_PC * JB_ELEMENT_SIZE, buf,
+ LONGJMP_TARGET_SIZE))
+ return 0;
+
+ *pc = extract_address (buf, LONGJMP_TARGET_SIZE);
+
+ return 1;
+}
+#endif /* GET_LONGJMP_TARGET */
+\f
+#ifdef STATIC_TRANSFORM_NAME
+/* SunPRO (3.0 at least), encodes the static variables. This is not
+ related to C++ mangling, it is done for C too. */
+
+char *
+sunpro_static_transform_name (name)
+ char *name;
+{
+ char *p;
+ if (name[0] == '$')
+ {
+ /* For file-local statics there will be a dollar sign, a bunch
+ of junk (the contents of which match a string given in the
+ N_OPT), a period and the name. For function-local statics
+ there will be a bunch of junk (which seems to change the
+ second character from 'A' to 'B'), a period, the name of the
+ function, and the name. So just skip everything before the
+ last period. */
+ p = strrchr (name, '.');
+ if (p != NULL)
+ name = p + 1;
+ }
+ return name;
+}
+#endif /* STATIC_TRANSFORM_NAME */
+\f
+
+/* Utilities for printing registers.
+ Page numbers refer to the SPARC Architecture Manual. */
+
+static void dump_ccreg PARAMS ((char *, int));
+
+static void
+dump_ccreg (reg, val)
+ char *reg;
+ int val;
+{
+ /* page 41 */
+ printf_unfiltered ("%s:%s,%s,%s,%s", reg,
+ val & 8 ? "N" : "NN",
+ val & 4 ? "Z" : "NZ",
+ val & 2 ? "O" : "NO",
+ val & 1 ? "C" : "NC"
+ );
+}
+
+static char *
+decode_asi (val)
+ int val;
+{
+ /* page 72 */
+ switch (val)
+ {
+ case 4:
+ return "ASI_NUCLEUS";
+ case 0x0c:
+ return "ASI_NUCLEUS_LITTLE";
+ case 0x10:
+ return "ASI_AS_IF_USER_PRIMARY";
+ case 0x11:
+ return "ASI_AS_IF_USER_SECONDARY";
+ case 0x18:
+ return "ASI_AS_IF_USER_PRIMARY_LITTLE";
+ case 0x19:
+ return "ASI_AS_IF_USER_SECONDARY_LITTLE";
+ case 0x80:
+ return "ASI_PRIMARY";
+ case 0x81:
+ return "ASI_SECONDARY";
+ case 0x82:
+ return "ASI_PRIMARY_NOFAULT";
+ case 0x83:
+ return "ASI_SECONDARY_NOFAULT";
+ case 0x88:
+ return "ASI_PRIMARY_LITTLE";
+ case 0x89:
+ return "ASI_SECONDARY_LITTLE";
+ case 0x8a:
+ return "ASI_PRIMARY_NOFAULT_LITTLE";
+ case 0x8b:
+ return "ASI_SECONDARY_NOFAULT_LITTLE";
+ default:
+ return NULL;
+ }
+}
+
+/* PRINT_REGISTER_HOOK routine.
+ Pretty print various registers. */
+/* FIXME: Would be nice if this did some fancy things for 32 bit sparc. */
+
+void
+sparc_print_register_hook (regno)
+ int regno;
+{
+ ULONGEST val;
+
+ /* Handle double/quad versions of lower 32 fp regs. */
+ if (regno >= FP0_REGNUM && regno < FP0_REGNUM + 32
+ && (regno & 1) == 0)
+ {
+ char value[16];
+
+ if (!read_relative_register_raw_bytes (regno, value)
+ && !read_relative_register_raw_bytes (regno + 1, value + 4))
+ {
+ printf_unfiltered ("\t");
+ print_floating (value, builtin_type_double, gdb_stdout);
+ }
+#if 0 /* FIXME: gdb doesn't handle long doubles */
+ if ((regno & 3) == 0)
+ {
+ if (!read_relative_register_raw_bytes (regno + 2, value + 8)
+ && !read_relative_register_raw_bytes (regno + 3, value + 12))
+ {
+ printf_unfiltered ("\t");
+ print_floating (value, builtin_type_long_double, gdb_stdout);
+ }
+ }
+#endif
+ return;
+ }
+
+#if 0 /* FIXME: gdb doesn't handle long doubles */
+ /* Print upper fp regs as long double if appropriate. */
+ if (regno >= FP0_REGNUM + 32 && regno < FP_MAX_REGNUM
+ /* We test for even numbered regs and not a multiple of 4 because
+ the upper fp regs are recorded as doubles. */
+ && (regno & 1) == 0)
+ {
+ char value[16];
+
+ if (!read_relative_register_raw_bytes (regno, value)
+ && !read_relative_register_raw_bytes (regno + 1, value + 8))
+ {
+ printf_unfiltered ("\t");
+ print_floating (value, builtin_type_long_double, gdb_stdout);
+ }
+ return;
+ }
+#endif
+
+ /* FIXME: Some of these are priviledged registers.
+ Not sure how they should be handled. */
+
+#define BITS(n, mask) ((int) (((val) >> (n)) & (mask)))
+
+ val = read_register (regno);
+
+ /* pages 40 - 60 */
+ switch (regno)
+ {
+#ifdef GDB_TARGET_IS_SPARC64
+ case CCR_REGNUM:
+ printf_unfiltered ("\t");
+ dump_ccreg ("xcc", val >> 4);
+ printf_unfiltered (", ");
+ dump_ccreg ("icc", val & 15);
+ break;
+ case FPRS_REGNUM:
+ printf ("\tfef:%d, du:%d, dl:%d",
+ BITS (2, 1), BITS (1, 1), BITS (0, 1));
+ break;
+ case FSR_REGNUM:
+ {
+ static char *fcc[4] =
+ {"=", "<", ">", "?"};
+ static char *rd[4] =
+ {"N", "0", "+", "-"};
+ /* Long, yes, but I'd rather leave it as is and use a wide screen. */
+ printf ("\t0:%s, 1:%s, 2:%s, 3:%s, rd:%s, tem:%d, ns:%d, ver:%d, ftt:%d, qne:%d, aexc:%d, cexc:%d",
+ fcc[BITS (10, 3)], fcc[BITS (32, 3)],
+ fcc[BITS (34, 3)], fcc[BITS (36, 3)],
+ rd[BITS (30, 3)], BITS (23, 31), BITS (22, 1), BITS (17, 7),
+ BITS (14, 7), BITS (13, 1), BITS (5, 31), BITS (0, 31));
+ break;
+ }
+ case ASI_REGNUM:
+ {
+ char *asi = decode_asi (val);
+ if (asi != NULL)
+ printf ("\t%s", asi);
+ break;
+ }
+ case VER_REGNUM:
+ printf ("\tmanuf:%d, impl:%d, mask:%d, maxtl:%d, maxwin:%d",
+ BITS (48, 0xffff), BITS (32, 0xffff),
+ BITS (24, 0xff), BITS (8, 0xff), BITS (0, 31));
+ break;
+ case PSTATE_REGNUM:
+ {
+ static char *mm[4] =
+ {"tso", "pso", "rso", "?"};
+ printf ("\tcle:%d, tle:%d, mm:%s, red:%d, pef:%d, am:%d, priv:%d, ie:%d, ag:%d",
+ BITS (9, 1), BITS (8, 1), mm[BITS (6, 3)], BITS (5, 1),
+ BITS (4, 1), BITS (3, 1), BITS (2, 1), BITS (1, 1),
+ BITS (0, 1));
+ break;
+ }
+ case TSTATE_REGNUM:
+ /* FIXME: print all 4? */
+ break;
+ case TT_REGNUM:
+ /* FIXME: print all 4? */
+ break;
+ case TPC_REGNUM:
+ /* FIXME: print all 4? */
+ break;
+ case TNPC_REGNUM:
+ /* FIXME: print all 4? */
+ break;
+ case WSTATE_REGNUM:
+ printf ("\tother:%d, normal:%d", BITS (3, 7), BITS (0, 7));
+ break;
+ case CWP_REGNUM:
+ printf ("\t%d", BITS (0, 31));
+ break;
+ case CANSAVE_REGNUM:
+ printf ("\t%-2d before spill", BITS (0, 31));
+ break;
+ case CANRESTORE_REGNUM:
+ printf ("\t%-2d before fill", BITS (0, 31));
+ break;
+ case CLEANWIN_REGNUM:
+ printf ("\t%-2d before clean", BITS (0, 31));
+ break;
+ case OTHERWIN_REGNUM:
+ printf ("\t%d", BITS (0, 31));
+ break;
+#else
+ case PS_REGNUM:
+ printf ("\ticc:%c%c%c%c, pil:%d, s:%d, ps:%d, et:%d, cwp:%d",
+ BITS (23, 1) ? 'N' : '-', BITS (22, 1) ? 'Z' : '-',
+ BITS (21, 1) ? 'V' : '-', BITS (20, 1) ? 'C' : '-',
+ BITS (8, 15), BITS (7, 1), BITS (6, 1), BITS (5, 1),
+ BITS (0, 31));
+ break;
+ case FPS_REGNUM:
+ {
+ static char *fcc[4] =
+ {"=", "<", ">", "?"};
+ static char *rd[4] =
+ {"N", "0", "+", "-"};
+ /* Long, yes, but I'd rather leave it as is and use a wide screen. */
+ printf ("\trd:%s, tem:%d, ns:%d, ver:%d, ftt:%d, qne:%d, "
+ "fcc:%s, aexc:%d, cexc:%d",
+ rd[BITS (30, 3)], BITS (23, 31), BITS (22, 1), BITS (17, 7),
+ BITS (14, 7), BITS (13, 1), fcc[BITS (10, 3)], BITS (5, 31),
+ BITS (0, 31));
+ break;
+ }
+
+#endif /* GDB_TARGET_IS_SPARC64 */
+ }
+
+#undef BITS
+}
+\f
+int
+gdb_print_insn_sparc (memaddr, info)
+ bfd_vma memaddr;
+ disassemble_info *info;
+{
+ /* It's necessary to override mach again because print_insn messes it up. */
+ info->mach = TARGET_ARCHITECTURE->mach;
+ return print_insn_sparc (memaddr, info);
+}
+\f
+/* The SPARC passes the arguments on the stack; arguments smaller
+ than an int are promoted to an int. */
+
+CORE_ADDR
+sparc_push_arguments (nargs, args, sp, struct_return, struct_addr)
+ int nargs;
+ value_ptr *args;
+ CORE_ADDR sp;
+ int struct_return;
+ CORE_ADDR struct_addr;
+{
+ int i;
+ int accumulate_size = 0;
+ struct sparc_arg
+ {
+ char *contents;
+ int len;
+ int offset;
+ };
+ struct sparc_arg *sparc_args =
+ (struct sparc_arg *) alloca (nargs * sizeof (struct sparc_arg));
+ struct sparc_arg *m_arg;
+
+ /* Promote arguments if necessary, and calculate their stack offsets
+ and sizes. */
+ for (i = 0, m_arg = sparc_args; i < nargs; i++, m_arg++)
+ {
+ value_ptr arg = args[i];
+ struct type *arg_type = check_typedef (VALUE_TYPE (arg));
+ /* Cast argument to long if necessary as the compiler does it too. */
+ switch (TYPE_CODE (arg_type))
+ {
+ case TYPE_CODE_INT:
+ case TYPE_CODE_BOOL:
+ case TYPE_CODE_CHAR:
+ case TYPE_CODE_RANGE:
+ case TYPE_CODE_ENUM:
+ if (TYPE_LENGTH (arg_type) < TYPE_LENGTH (builtin_type_long))
+ {
+ arg_type = builtin_type_long;
+ arg = value_cast (arg_type, arg);
+ }
+ break;
+ default:
+ break;
+ }
+ m_arg->len = TYPE_LENGTH (arg_type);
+ m_arg->offset = accumulate_size;
+ accumulate_size = (accumulate_size + m_arg->len + 3) & ~3;
+ m_arg->contents = VALUE_CONTENTS (arg);
+ }
+
+ /* Make room for the arguments on the stack. */
+ accumulate_size += CALL_DUMMY_STACK_ADJUST;
+ sp = ((sp - accumulate_size) & ~7) + CALL_DUMMY_STACK_ADJUST;
+
+ /* `Push' arguments on the stack. */
+ for (i = nargs; m_arg--, --i >= 0;)
+ write_memory (sp + m_arg->offset, m_arg->contents, m_arg->len);
+
+ return sp;
+}
+
+
+/* Extract from an array REGBUF containing the (raw) register state
+ a function return value of type TYPE, and copy that, in virtual format,
+ into VALBUF. */
+
+void
+sparc_extract_return_value (type, regbuf, valbuf)
+ struct type *type;
+ char *regbuf;
+ char *valbuf;
+{
+ int typelen = TYPE_LENGTH (type);
+ int regsize = REGISTER_RAW_SIZE (O0_REGNUM);
+
+ if (TYPE_CODE (type) == TYPE_CODE_FLT && SPARC_HAS_FPU)
+ memcpy (valbuf, ®buf[REGISTER_BYTE (FP0_REGNUM)], typelen);
+ else
+ memcpy (valbuf,
+ ®buf[O0_REGNUM * regsize +
+ (typelen >= regsize
+ || TARGET_BYTE_ORDER == LITTLE_ENDIAN ? 0
+ : regsize - typelen)],
+ typelen);
+}
+
+
+/* Write into appropriate registers a function return value
+ of type TYPE, given in virtual format. On SPARCs with FPUs,
+ float values are returned in %f0 (and %f1). In all other cases,
+ values are returned in register %o0. */
+
+void
+sparc_store_return_value (type, valbuf)
+ struct type *type;
+ char *valbuf;
+{
+ int regno;
+ char buffer[MAX_REGISTER_RAW_SIZE];
+
+ if (TYPE_CODE (type) == TYPE_CODE_FLT && SPARC_HAS_FPU)
+ /* Floating-point values are returned in the register pair */
+ /* formed by %f0 and %f1 (doubles are, anyway). */
+ regno = FP0_REGNUM;
+ else
+ /* Other values are returned in register %o0. */
+ regno = O0_REGNUM;
+
+ /* Add leading zeros to the value. */
+ if (TYPE_LENGTH (type) < REGISTER_RAW_SIZE (regno))
+ {
+ bzero (buffer, REGISTER_RAW_SIZE (regno));
+ memcpy (buffer + REGISTER_RAW_SIZE (regno) - TYPE_LENGTH (type), valbuf,
+ TYPE_LENGTH (type));
+ write_register_bytes (REGISTER_BYTE (regno), buffer,
+ REGISTER_RAW_SIZE (regno));
+ }
+ else
+ write_register_bytes (REGISTER_BYTE (regno), valbuf, TYPE_LENGTH (type));
+}
+
+
+/* Insert the function address into a call dummy instruction sequence
+ stored at DUMMY.
+
+ For structs and unions, if the function was compiled with Sun cc,
+ it expects 'unimp' after the call. But gcc doesn't use that
+ (twisted) convention. So leave a nop there for gcc (FIX_CALL_DUMMY
+ can assume it is operating on a pristine CALL_DUMMY, not one that
+ has already been customized for a different function). */
+
+void
+sparc_fix_call_dummy (dummy, pc, fun, value_type, using_gcc)
+ char *dummy;
+ CORE_ADDR pc;
+ CORE_ADDR fun;
+ struct type *value_type;
+ int using_gcc;
+{
+ int i;
+
+ /* Store the relative adddress of the target function into the
+ 'call' instruction. */
+ store_unsigned_integer (dummy + CALL_DUMMY_CALL_OFFSET, 4,
+ (0x40000000
+ | (((fun - (pc + CALL_DUMMY_CALL_OFFSET)) >> 2)
+ & 0x3fffffff)));
+
+ /* Comply with strange Sun cc calling convention for struct-returning
+ functions. */
+ if (!using_gcc
+ && (TYPE_CODE (value_type) == TYPE_CODE_STRUCT
+ || TYPE_CODE (value_type) == TYPE_CODE_UNION))
+ store_unsigned_integer (dummy + CALL_DUMMY_CALL_OFFSET + 8, 4,
+ TYPE_LENGTH (value_type) & 0x1fff);
+
+#ifndef GDB_TARGET_IS_SPARC64
+ /* If this is not a simulator target, change the first four instructions
+ of the call dummy to NOPs. Those instructions include a 'save'
+ instruction and are designed to work around problems with register
+ window flushing in the simulator. */
+ if (strcmp (target_shortname, "sim") != 0)
+ {
+ for (i = 0; i < 4; i++)
+ store_unsigned_integer (dummy + (i * 4), 4, 0x01000000);
+ }
+#endif
+
+ /* If this is a bi-endian target, GDB has written the call dummy
+ in little-endian order. We must byte-swap it back to big-endian. */
+ if (bi_endian)
+ {
+ for (i = 0; i < CALL_DUMMY_LENGTH; i += 4)
+ {
+ char tmp = dummy[i];
+ dummy[i] = dummy[i + 3];
+ dummy[i + 3] = tmp;
+ tmp = dummy[i + 1];
+ dummy[i + 1] = dummy[i + 2];
+ dummy[i + 2] = tmp;
+ }
+ }
+}
+
+
+/* Set target byte order based on machine type. */
+
+static int
+sparc_target_architecture_hook (ap)
+ const bfd_arch_info_type *ap;
+{
+ int i, j;
+
+ if (ap->mach == bfd_mach_sparc_sparclite_le)
+ {
+ if (TARGET_BYTE_ORDER_SELECTABLE_P)
+ {
+ target_byte_order = LITTLE_ENDIAN;
+ bi_endian = 1;
+ }
+ else
+ {
+ warning ("This GDB does not support little endian sparclite.");
+ }
+ }
+ else
+ bi_endian = 0;
+ return 1;
+}
+\f
+
+void
+_initialize_sparc_tdep ()
+{
+ tm_print_insn = gdb_print_insn_sparc;
+ tm_print_insn_info.mach = TM_PRINT_INSN_MACH; /* Selects sparc/sparclite */
+ target_architecture_hook = sparc_target_architecture_hook;
+}
+
+
+#ifdef GDB_TARGET_IS_SPARC64
+
+/* Compensate for stack bias. Note that we currently don't handle mixed
+ 32/64 bit code. */
+CORE_ADDR
+sparc64_read_sp ()
+{
+ CORE_ADDR sp = read_register (SP_REGNUM);
+
+ if (sp & 1)
+ sp += 2047;
+ return sp;
+}
+
+CORE_ADDR
+sparc64_read_fp ()
+{
+ CORE_ADDR fp = read_register (FP_REGNUM);
+
+ if (fp & 1)
+ fp += 2047;
+ return fp;
+}
+
+void
+sparc64_write_sp (val)
+ CORE_ADDR val;
+{
+ CORE_ADDR oldsp = read_register (SP_REGNUM);
+ if (oldsp & 1)
+ write_register (SP_REGNUM, val - 2047);
+ else
+ write_register (SP_REGNUM, val);
+}
+
+void
+sparc64_write_fp (val)
+ CORE_ADDR val;
+{
+ CORE_ADDR oldfp = read_register (FP_REGNUM);
+ if (oldfp & 1)
+ write_register (FP_REGNUM, val - 2047);
+ else
+ write_register (FP_REGNUM, val);
+}
+
+/* The SPARC 64 ABI passes floating-point arguments in FP0-31. They are
+ also copied onto the stack in the correct places. */
+
+CORE_ADDR
+sp64_push_arguments (nargs, args, sp, struct_return, struct_retaddr)
+ int nargs;
+ value_ptr *args;
+ CORE_ADDR sp;
+ unsigned char struct_return;
+ CORE_ADDR struct_retaddr;
+{
+ int x;
+ int regnum = 0;
+ CORE_ADDR tempsp;
+
+ sp = (sp & ~(((unsigned long) TYPE_LENGTH (builtin_type_long)) - 1UL));
+
+ /* Figure out how much space we'll need. */
+ for (x = nargs - 1; x >= 0; x--)
+ {
+ int len = TYPE_LENGTH (check_typedef (VALUE_TYPE (args[x])));
+ value_ptr copyarg = args[x];
+ int copylen = len;
+
+ /* This code is, of course, no longer correct. */
+ if (copylen < TYPE_LENGTH (builtin_type_long))
+ {
+ copyarg = value_cast (builtin_type_long, copyarg);
+ copylen = TYPE_LENGTH (builtin_type_long);
+ }
+ sp -= copylen;
+ }
+
+ /* Round down. */
+ sp = sp & ~7;
+ tempsp = sp;
+
+ /* Now write the arguments onto the stack, while writing FP arguments
+ into the FP registers. */
+ for (x = 0; x < nargs; x++)
+ {
+ int len = TYPE_LENGTH (check_typedef (VALUE_TYPE (args[x])));
+ value_ptr copyarg = args[x];
+ int copylen = len;
+
+ /* This code is, of course, no longer correct. */
+ if (copylen < TYPE_LENGTH (builtin_type_long))
+ {
+ copyarg = value_cast (builtin_type_long, copyarg);
+ copylen = TYPE_LENGTH (builtin_type_long);
+ }
+ write_memory (tempsp, VALUE_CONTENTS (copyarg), copylen);
+ tempsp += copylen;
+ if (TYPE_CODE (VALUE_TYPE (args[x])) == TYPE_CODE_FLT && regnum < 32)
+ {
+ /* This gets copied into a FP register. */
+ int nextreg = regnum + 2;
+ char *data = VALUE_CONTENTS (args[x]);
+ /* Floats go into the lower half of a FP register pair; quads
+ use 2 pairs. */
+
+ if (len == 16)
+ nextreg += 2;
+ else if (len == 4)
+ regnum++;
+
+ write_register_bytes (REGISTER_BYTE (FP0_REGNUM + regnum),
+ data,
+ len);
+ regnum = nextreg;
+ }
+ }
+ return sp;
+}
+
+/* Values <= 32 bytes are returned in o0-o3 (floating-point values are
+ returned in f0-f3). */
+void
+sparc64_extract_return_value (type, regbuf, valbuf, bitoffset)
+ struct type *type;
+ char *regbuf;
+ char *valbuf;
+ int bitoffset;
+{
+ int typelen = TYPE_LENGTH (type);
+ int regsize = REGISTER_RAW_SIZE (O0_REGNUM);
+
+ if (TYPE_CODE (type) == TYPE_CODE_FLT && SPARC_HAS_FPU)
+ {
+ memcpy (valbuf, ®buf[REGISTER_BYTE (FP0_REGNUM)], typelen);
+ return;
+ }
+
+ if (TYPE_CODE (type) != TYPE_CODE_STRUCT
+ || (TYPE_LENGTH (type) > 32))
+ {
+ memcpy (valbuf,
+ ®buf[O0_REGNUM * regsize +
+ (typelen >= regsize ? 0 : regsize - typelen)],
+ typelen);
+ return;
+ }
+ else
+ {
+ char *o0 = ®buf[O0_REGNUM * regsize];
+ char *f0 = ®buf[FP0_REGNUM * regsize];
+ int x;
+
+ for (x = 0; x < TYPE_NFIELDS (type); x++)
+ {
+ struct field *f = &TYPE_FIELDS (type)[x];
+ /* FIXME: We may need to handle static fields here. */
+ int whichreg = (f->loc.bitpos + bitoffset) / 32;
+ int remainder = ((f->loc.bitpos + bitoffset) % 32) / 8;
+ int where = (f->loc.bitpos + bitoffset) / 8;
+ int size = TYPE_LENGTH (f->type);
+ int typecode = TYPE_CODE (f->type);
+
+ if (typecode == TYPE_CODE_STRUCT)
+ {
+ sparc64_extract_return_value (f->type,
+ regbuf,
+ valbuf,
+ bitoffset + f->loc.bitpos);
+ }
+ else if (typecode == TYPE_CODE_FLT)
+ {
+ memcpy (valbuf + where, &f0[whichreg * 4] + remainder, size);
+ }
+ else
+ {
+ memcpy (valbuf + where, &o0[whichreg * 4] + remainder, size);
+ }
+ }
+ }
+}
+