+ DEFINE_bool(pic_veneer, options::TWO_DASHES, '\0', false,
+ N_("Force PIC sequences for ARM/Thumb interworking veneers"),
+ NULL);
+
+ DEFINE_bool(pipeline_knowledge, options::ONE_DASH, '\0', false,
+ NULL, N_("(ARM only) Ignore for backward compatibility"));
+
+ DEFINE_var(plt_align, options::TWO_DASHES, '\0', 0, "5",
+ N_("(PowerPC64 only) Align PLT call stubs to fit cache lines"),
+ N_("[=P2ALIGN]"), true, int, int, options::parse_uint, false);
+
+ DEFINE_bool(plt_localentry, options::TWO_DASHES, '\0', false,
+ N_("(PowerPC64 only) Optimize calls to ELFv2 localentry:0 functions"),
+ N_("(PowerPC64 only) Don't optimize ELFv2 calls"));
+
+ DEFINE_bool(plt_static_chain, options::TWO_DASHES, '\0', false,
+ N_("(PowerPC64 only) PLT call stubs should load r11"),
+ N_("(PowerPC64 only) PLT call stubs should not load r11"));
+
+ DEFINE_bool(plt_thread_safe, options::TWO_DASHES, '\0', false,
+ N_("(PowerPC64 only) PLT call stubs with load-load barrier"),
+ N_("(PowerPC64 only) PLT call stubs without barrier"));
+