+template<int size>
+static bool
+relative_value_is_known(const Sized_symbol<size>* gsym)
+{
+ if (gsym->type() == elfcpp::STT_GNU_IFUNC)
+ return false;
+
+ if (gsym->is_from_dynobj()
+ || gsym->is_undefined()
+ || gsym->is_preemptible())
+ return false;
+
+ if (gsym->is_absolute())
+ return !parameters->options().output_is_position_independent();
+
+ return true;
+}
+
+template<int size>
+static bool
+relative_value_is_known(const Symbol_value<size>* psymval)
+{
+ if (psymval->is_ifunc_symbol())
+ return false;
+
+ bool is_ordinary;
+ unsigned int shndx = psymval->input_shndx(&is_ordinary);
+
+ return is_ordinary && shndx != elfcpp::SHN_UNDEF;
+}
+
+// PCREL_OPT in one instance flags to the linker that a pair of insns:
+// pld ra,symbol@got@pcrel
+// load/store rt,0(ra)
+// or
+// pla ra,symbol@pcrel
+// load/store rt,0(ra)
+// may be translated to
+// pload/pstore rt,symbol@pcrel
+// nop.
+// This function returns true if the optimization is possible, placing
+// the prefix insn in *PINSN1 and a NOP in *PINSN2.
+//
+// On entry to this function, the linker has already determined that
+// the pld can be replaced with pla: *PINSN1 is that pla insn,
+// while *PINSN2 is the second instruction.
+
+inline bool
+xlate_pcrel_opt(uint64_t *pinsn1, uint64_t *pinsn2)
+{
+ uint32_t insn2 = *pinsn2 >> 32;
+ uint64_t i1new;
+
+ // Check that regs match.
+ if (((insn2 >> 16) & 31) != ((*pinsn1 >> 21) & 31))
+ return false;
+
+ switch ((insn2 >> 26) & 63)
+ {
+ default:
+ return false;
+
+ case 32: // lwz
+ case 34: // lbz
+ case 36: // stw
+ case 38: // stb
+ case 40: // lhz
+ case 42: // lha
+ case 44: // sth
+ case 48: // lfs
+ case 50: // lfd
+ case 52: // stfs
+ case 54: // stfd
+ // These are the PMLS cases, where we just need to tack a prefix
+ // on the insn. Check that the D field is zero.
+ if ((insn2 & 0xffff) != 0)
+ return false;
+ i1new = ((1ULL << 58) | (2ULL << 56) | (1ULL << 52)
+ | (insn2 & ((63ULL << 26) | (31ULL << 21))));
+ break;
+
+ case 58: // lwa, ld
+ if ((insn2 & 0xfffd) != 0)
+ return false;
+ i1new = ((1ULL << 58) | (1ULL << 52)
+ | (insn2 & 2 ? 41ULL << 26 : 57ULL << 26)
+ | (insn2 & (31ULL << 21)));
+ break;
+
+ case 57: // lxsd, lxssp
+ if ((insn2 & 0xfffc) != 0 || (insn2 & 3) < 2)
+ return false;
+ i1new = ((1ULL << 58) | (1ULL << 52)
+ | ((40ULL | (insn2 & 3)) << 26)
+ | (insn2 & (31ULL << 21)));
+ break;
+
+ case 61: // stxsd, stxssp, lxv, stxv
+ if ((insn2 & 3) == 0)
+ return false;
+ else if ((insn2 & 3) >= 2)
+ {
+ if ((insn2 & 0xfffc) != 0)
+ return false;
+ i1new = ((1ULL << 58) | (1ULL << 52)
+ | ((44ULL | (insn2 & 3)) << 26)
+ | (insn2 & (31ULL << 21)));
+ }
+ else
+ {
+ if ((insn2 & 0xfff0) != 0)
+ return false;
+ i1new = ((1ULL << 58) | (1ULL << 52)
+ | ((50ULL | (insn2 & 4) | ((insn2 & 8) >> 3)) << 26)
+ | (insn2 & (31ULL << 21)));
+ }
+ break;
+
+ case 56: // lq
+ if ((insn2 & 0xffff) != 0)
+ return false;
+ i1new = ((1ULL << 58) | (1ULL << 52)
+ | (insn2 & ((63ULL << 26) | (31ULL << 21))));
+ break;
+
+ case 62: // std, stq
+ if ((insn2 & 0xfffd) != 0)
+ return false;
+ i1new = ((1ULL << 58) | (1ULL << 52)
+ | ((insn2 & 2) == 0 ? 61ULL << 26 : 60ULL << 26)
+ | (insn2 & (31ULL << 21)));
+ break;
+ }
+
+ *pinsn1 = i1new;
+ *pinsn2 = (uint64_t) nop << 32;
+ return true;
+}
+