+#define TIC80_OPERAND_BASEREL (1u << 11)
+
+/* This operand is an "endmask" field for a shift instruction.
+ It is treated special in that it can have values of 0-32,
+ where 0 and 32 result in the same instruction. The assembler
+ must be able to accept both endmask values. This disassembler
+ has no way of knowing from the instruction which value was
+ given at assembly time, so it just uses '0'. */
+
+#define TIC80_OPERAND_ENDMASK (1u << 12)
+
+/* This operand is one of the 32 general purpose registers.
+ The disassembler prints these with a leading 'r'. */
+
+#define TIC80_OPERAND_GPR (1u << 27)
+
+/* This operand is a floating point accumulator register.
+ The disassembler prints these with a leading 'a'. */
+
+#define TIC80_OPERAND_FPA (1u << 28)
+
+/* This operand is a control register number, either numeric or
+ symbolic (like "EIF", "EPC", etc).
+ The disassembler prints these symbolically. */
+
+#define TIC80_OPERAND_CR (1u << 29)
+
+/* This operand is a condition code, either numeric or
+ symbolic (like "eq0.b", "ne0.w", etc).
+ The disassembler prints these symbolically. */
+
+#define TIC80_OPERAND_CC (1u << 30)
+
+/* This operand is a bit number, either numeric or
+ symbolic (like "eq.b", "or.f", etc).
+ The disassembler prints these symbolically.
+ Note that they appear in the instruction in 1's complement relative
+ to the values given in the manual. */
+
+#define TIC80_OPERAND_BITNUM (1u << 31)
+
+/* This mask is used to strip operand bits from an int that contains
+ both operand bits and a numeric value in the lsbs. */
+
+#define TIC80_OPERAND_MASK (TIC80_OPERAND_GPR | TIC80_OPERAND_FPA | TIC80_OPERAND_CR | TIC80_OPERAND_CC | TIC80_OPERAND_BITNUM)
+
+\f