+ if (caa_likely(rseq_state.cpu_id >= 0)) {
+ unsigned long newv;
+
+ newv = cc_hot->cc_rseq + ctx->slot_size;
+ if (caa_likely(__rseq_finish(NULL, 0, NULL, NULL, 0,
+ (intptr_t *)&cc_hot->cc_rseq,
+ (intptr_t) newv,
+ rseq_state, RSEQ_FINISH_SINGLE, false)))
+ goto add_done;
+ }