- * arm-dis.c (arm_opcodes): SMC implies Security Extensions.
- (thumb32_opcodes): Likewise.
-
-2010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
-
- * arm-dis.c (arm_opcodes): Add support for pldw.
- (thumb32_opcodes): Likewise.
-
-2010-09-22 Robin Getz <robin.getz@analog.com>
-
- * bfin-dis.c (fmtconst): Cast address to 32bits.
-
-2010-09-22 Mike Frysinger <vapier@gentoo.org>
-
- * bfin-dis.c (decode_REGMV_0): Rewrite valid combo checks.
-
-2010-09-22 Robin Getz <robin.getz@analog.com>
-
- * bfin-dis.c (decode_ProgCtrl_0): Check for parallel insns.
- Reject P6/P7 to TESTSET.
- (decode_PushPopReg_0): Check for parallel insns. Reject pushing
- SP onto the stack.
- (decode_PushPopMultiple_0): Check for parallel insns. Make sure
- P/D fields match all the time.
- (decode_CCflag_0): Check for parallel insns. Verify x/y fields
- are 0 for accumulator compares.
- (decode_CC2stat_0): Check for parallel insns. Reject CC<op>CC.
- (decode_CaCTRL_0, decode_ccMV_0, decode_CC2dreg_0, decode_BRCC_0,
- decode_UJUMP_0, decode_LOGI2op_0, decode_COMPI2opD_0,
- decode_COMPI2opP_0, decode_LoopSetup_0, decode_LDIMMhalf_0,
- decode_CALLa_0, decode_linkage_0, decode_pseudoDEBUG_0,
- decode_pseudoOChar_0, decode_pseudodbg_assert_0): Check for parallel
- insns.
- (decode_dagMODim_0): Verify br field for IREG ops.
- (decode_LDST_0): Reject preg load into same preg.
- (_print_insn_bfin): Handle returns for ILLEGAL decodes.
- (print_insn_bfin): Likewise.
-
-2010-09-22 Mike Frysinger <vapier@gentoo.org>
-
- * bfin-dis.c (decode_PushPopMultiple_0): Return 0 when pr > 5.
-
-2010-09-22 Robin Getz <robin.getz@analog.com>
-
- * bfin-dis.c (decode_dsp32shiftimm_0): Add missing "S" flag.
-
-2010-09-22 Mike Frysinger <vapier@gentoo.org>
-
- * bfin-dis.c (decode_CC2stat_0): Decode all ASTAT bits.
-
-2010-09-22 Robin Getz <robin.getz@analog.com>
-
- * bfin-dis.c (IS_DREG, IS_PREG, IS_GENREG, IS_DAGREG): Reject
- register values greater than 8.
- (IS_RESERVEDREG, allreg, mostreg): New helpers.
- (decode_ProgCtrl_0): Call IS_DREG/IS_PREG as appropriate.
- (decode_PushPopReg_0): Call mostreg/allreg as appropriate.
- (decode_CC2dreg_0): Check valid CC register number.
-
-2010-09-22 Robin Getz <robin.getz@analog.com>
-
- * bfin-dis.c (decode_pseudoDEBUG_0): Add space after DBG.
-
-2010-09-22 Robin Getz <robin.getz@analog.com>
-
- * bfin-dis.c (machine_registers): Add AC0_COPY, V_COPY, and RND_MOD.
- (reg_names): Likewise.
- (decode_statbits): Likewise; while reformatting to make manageable.
-
-2010-09-22 Mike Frysinger <vapier@gentoo.org>
-
- * bfin-dis.c (decode_pseudoDEBUG_0): Add space after OUTC.
- (decode_pseudoOChar_0): New function.
- (_print_insn_bfin): Remove #if 0 and call new decode_pseudoOChar_0.
-
-2010-09-22 Robin Getz <robin.getz@analog.com>
-
- * bfin-dis.c (decode_dsp32shift_0): Decode sub opcodes 2/2 as
- LSHIFT instead of SHIFT.
-
-2010-09-22 Mike Frysinger <vapier@gentoo.org>
-
- * bfin-dis.c (constant_formats): Constify the whole structure.
- (fmtconst): Add const to return value.
- (reg_names): Mark const.
- (decode_multfunc): Mark s0/s1 as const.
- (decode_macfunc): Mark a/sop as const.
-
-2010-09-17 Tejas Belagod <tejas.belagod@arm.com>
-
- * arm_dis.c (coprocessor_opcodes): Add MRC entry for APSR_nzcv.
-
-2010-09-14 Maciej W. Rozycki <macro@codesourcery.com>
-
- * mips-opc.c (mips_builtin_opcodes): Add "sync_acquire",
- "sync_mb", "sync_release", "sync_rmb" and "sync_wmb".
-
-2010-09-10 Pierre Muller <muller@ics.u-strasbg.fr>
-
- * src/opcodes/dlx-dis.c (print_insn_dlx): Use dlx_insn type for
- dlx_insn_type array.
-
-2010-08-31 H.J. Lu <hongjiu.lu@intel.com>
-
- PR binutils/11960
- * i386-dis.c (sIv): New.
- (dis386): Replace Iq with sIv on "pushT".
- (reg_table): Replace T with {T|} on callT, JcallT, jmpT and JjmpT.
- (x86_64_table): Replace {T|}/{P|} with P.
- (putop): Add 'w' to 'T'/'P' if needed for Intel syntax.
- (OP_sI): Update v_mode. Remove w_mode.
-
-2010-08-27 Nathan Froyd <froydnj@codesourcery.com>
-
- * ppc-opc.c (powerpc_opcodes) [lswx,lswi,stswx,stswi]: Deprecate
- on E500 and E500MC.
-
-2010-08-17 H.J. Lu <hongjiu.lu@intel.com>
-
- * i386-dis.c (reg_table): Replace Eb with Mb on prefetch and
- prefetchw.
-
-2010-08-06 Quentin Neill <quentin.neill@amd.com>
+ * Makefile.am (TARGET_LIBOPCODES_CFILES): Add tilegx-dis.c,
+ tilegx-opc.c, tilepro-dis.c, and tilepro-opc.c.
+ * Makefile.in: Regenerate.
+ * configure.in: Handle bfd_tilegx_arch and bfd_tilepro_arch.
+ * configure: Regenerate.
+ * disassemble.c (disassembler): Add ARCH_tilegx and ARCH_tilepro.
+ * po/POTFILES.in: Regenerate.
+ * tilegx-dis.c: New file.
+ * tilegx-opc.c: New file.
+ * tilepro-dis.c: New file.
+ * tilepro-opc.c: New file.
+
+2011-06-10 H.J. Lu <hongjiu.lu@intel.com>
+
+ AVX Programming Reference (June, 2011)
+ * i386-dis.c (XMGatherQ): New.
+ * i386-dis.c (EXxmm_mb): New.
+ (EXxmm_mb): Likewise.
+ (EXxmm_mw): Likewise.
+ (EXxmm_md): Likewise.
+ (EXxmm_mq): Likewise.
+ (EXxmmdw): Likewise.
+ (EXxmmqd): Likewise.
+ (VexGatherQ): Likewise.
+ (MVexVSIBDWpX): Likewise.
+ (MVexVSIBQWpX): Likewise.
+ (xmm_mb_mode): Likewise.
+ (xmm_mw_mode): Likewise.
+ (xmm_md_mode): Likewise.
+ (xmm_mq_mode): Likewise.
+ (xmmdw_mode): Likewise.
+ (xmmqd_mode): Likewise.
+ (ymmxmm_mode): Likewise.
+ (vex_vsib_d_w_dq_mode): Likewise.
+ (vex_vsib_q_w_dq_mode): Likewise.
+ (MOD_VEX_0F385A_PREFIX_2): Likewise.
+ (MOD_VEX_0F388C_PREFIX_2): Likewise.
+ (MOD_VEX_0F388E_PREFIX_2): Likewise.
+ (PREFIX_0F3882): Likewise.
+ (PREFIX_VEX_0F3816): Likewise.
+ (PREFIX_VEX_0F3836): Likewise.
+ (PREFIX_VEX_0F3845): Likewise.
+ (PREFIX_VEX_0F3846): Likewise.
+ (PREFIX_VEX_0F3847): Likewise.
+ (PREFIX_VEX_0F3858): Likewise.
+ (PREFIX_VEX_0F3859): Likewise.
+ (PREFIX_VEX_0F385A): Likewise.
+ (PREFIX_VEX_0F3878): Likewise.
+ (PREFIX_VEX_0F3879): Likewise.
+ (PREFIX_VEX_0F388C): Likewise.
+ (PREFIX_VEX_0F388E): Likewise.
+ (PREFIX_VEX_0F3890..PREFIX_VEX_0F3893): Likewise.
+ (PREFIX_VEX_0F38F5): Likewise.
+ (PREFIX_VEX_0F38F6): Likewise.
+ (PREFIX_VEX_0F3A00): Likewise.
+ (PREFIX_VEX_0F3A01): Likewise.
+ (PREFIX_VEX_0F3A02): Likewise.
+ (PREFIX_VEX_0F3A38): Likewise.
+ (PREFIX_VEX_0F3A39): Likewise.
+ (PREFIX_VEX_0F3A46): Likewise.
+ (PREFIX_VEX_0F3AF0): Likewise.
+ (VEX_LEN_0F3816_P_2): Likewise.
+ (VEX_LEN_0F3819_P_2): Likewise.
+ (VEX_LEN_0F3836_P_2): Likewise.
+ (VEX_LEN_0F385A_P_2_M_0): Likewise.
+ (VEX_LEN_0F38F5_P_0): Likewise.
+ (VEX_LEN_0F38F5_P_1): Likewise.
+ (VEX_LEN_0F38F5_P_3): Likewise.
+ (VEX_LEN_0F38F6_P_3): Likewise.
+ (VEX_LEN_0F38F7_P_1): Likewise.
+ (VEX_LEN_0F38F7_P_2): Likewise.
+ (VEX_LEN_0F38F7_P_3): Likewise.
+ (VEX_LEN_0F3A00_P_2): Likewise.
+ (VEX_LEN_0F3A01_P_2): Likewise.
+ (VEX_LEN_0F3A38_P_2): Likewise.
+ (VEX_LEN_0F3A39_P_2): Likewise.
+ (VEX_LEN_0F3A46_P_2): Likewise.
+ (VEX_LEN_0F3AF0_P_3): Likewise.
+ (VEX_W_0F3816_P_2): Likewise.
+ (VEX_W_0F3818_P_2): Likewise.
+ (VEX_W_0F3819_P_2): Likewise.
+ (VEX_W_0F3836_P_2): Likewise.
+ (VEX_W_0F3846_P_2): Likewise.
+ (VEX_W_0F3858_P_2): Likewise.
+ (VEX_W_0F3859_P_2): Likewise.
+ (VEX_W_0F385A_P_2_M_0): Likewise.
+ (VEX_W_0F3878_P_2): Likewise.
+ (VEX_W_0F3879_P_2): Likewise.
+ (VEX_W_0F3A00_P_2): Likewise.
+ (VEX_W_0F3A01_P_2): Likewise.
+ (VEX_W_0F3A02_P_2): Likewise.
+ (VEX_W_0F3A38_P_2): Likewise.
+ (VEX_W_0F3A39_P_2): Likewise.
+ (VEX_W_0F3A46_P_2): Likewise.
+ (MOD_VEX_0F3818_PREFIX_2): Removed.
+ (MOD_VEX_0F3819_PREFIX_2): Likewise.
+ (VEX_LEN_0F60_P_2..VEX_LEN_0F6D_P_2): Likewise.
+ (VEX_LEN_0F70_P_1..VEX_LEN_0F76_P_2): Likewise.
+ (VEX_LEN_0FD1_P_2..VEX_LEN_0FD5_P_2): Likewise.
+ (VEX_LEN_0FD7_P_2_M_1..VEX_LEN_0F3819_P_2_M_0): Likewise.
+ (VEX_LEN_0F381C_P_2..VEX_LEN_0F3840_P_2): Likewise.
+ (VEX_LEN_0F3A0E_P_2): Likewise.
+ (VEX_LEN_0F3A0F_P_2): Likewise.
+ (VEX_LEN_0F3A42_P_2): Likewise.
+ (VEX_LEN_0F3A4C_P_2): Likewise.
+ (VEX_W_0F3818_P_2_M_0): Likewise.
+ (VEX_W_0F3819_P_2_M_0): Likewise.
+ (prefix_table): Updated.
+ (three_byte_table): Likewise.
+ (vex_table): Likewise.
+ (vex_len_table): Likewise.
+ (vex_w_table): Likewise.
+ (mod_table): Likewise.
+ (putop): Handle "LW".
+ (intel_operand_size): Handle xmm_mb_mode, xmm_mw_mode,
+ xmm_md_mode, xmm_mq_mode, xmmdw_mode, xmmqd_mode, ymmxmm_mode,
+ vex_vsib_d_w_dq_mode, vex_vsib_q_w_dq_mode.
+ (OP_EX): Likewise.
+ (OP_E_memory): Handle vex_vsib_d_w_dq_mode and
+ vex_vsib_q_w_dq_mode.
+ (OP_XMM): Handle vex_vsib_q_w_dq_mode.
+ (OP_VEX): Likewise.