- (xbegin): Drop DefaultSize.
- * i386-tbl.h: Re-generate.
-
-2019-11-22 Mihail Ionescu <mihail.ionescu@arm.com>
-
- * opcodes/arm-dis.c (arm_opcodes, thumb32_opcodes):
- Change the coproc CRC conditions to use the extension
- feature set, second word, base on ARM_EXT2_CRC.
-
-2019-11-14 Jan Beulich <jbeulich@suse.com>
-
- * i386-opc.tbl (syscall, sysret): Drop Cpu64 forms.
- * i386-tbl.h: Re-generate.
-
-2019-11-14 Jan Beulich <jbeulich@suse.com>
-
- * i386-gen.c (opcode_modifiers): Remove JumpDword, JumpByte,
- JumpInterSegment, and JumpAbsolute entries.
- * i386-opc.h (JUMP, JUMP_DWORD, JUMP_BYTE, JUMP_INTERSEGMENT,
- JUMP_ABSOLUTE): Define.
- (struct i386_opcode_modifier): Extend jump field to 3 bits.
- Remove jumpdword, jumpbyte, jumpintersegment, and jumpabsolute
- fields.
- * i386-opc.tbl (JumpByte, JumpDword, JumpAbsolute,
- JumpInterSegment): Define.
- * i386-tbl.h: Re-generate.
-
-2019-11-14 Jan Beulich <jbeulich@suse.com>
-
- * i386-gen.c (operand_type_init): Remove
- OPERAND_TYPE_JUMPABSOLUTE entry.
- (opcode_modifiers): Add JumpAbsolute entry.
- (operand_types): Remove JumpAbsolute entry.
- * i386-opc.h (JumpAbsolute): Move between enums.
- (struct i386_opcode_modifier): Add jumpabsolute field.
- (union i386_operand_type): Remove jumpabsolute field.
- * i386-opc.tbl (call, lcall, jmp, ljmp): Move JumpAbsolute.
- * i386-init.h, i386-tbl.h: Re-generate.
-
-2019-11-14 Jan Beulich <jbeulich@suse.com>
-
- * i386-gen.c (opcode_modifiers): Add AnySize entry.
- (operand_types): Remove AnySize entry.
- * i386-opc.h (AnySize): Move between enums.
- (struct i386_opcode_modifier): Add anysize field.
- (OTUnused): Un-comment.
- (union i386_operand_type): Remove anysize field.
- * i386-opc.tbl (lea, invlpg, clflush, prefetchnta, prefetcht0,
- prefetcht1, prefetcht2, prefetchtw, bndmk, bndcl, bndcu, bndcn,
- bndstx, bndldx, prefetchwt1, clflushopt, clwb, cldemote): Move
- AnySize.
- * i386-tbl.h: Re-generate.
-
-2019-11-12 Nelson Chu <nelson.chu@sifive.com>
-
- * riscv-opc.c (riscv_insn_types): Replace the INSN_CLASS_I with
- INSN_CLASS_F and the INSN_CLASS_C with INSN_CLASS_F_AND_C if we
- use the floating point register (FPR).
-
-2019-11-12 Mihail Ionescu <mihail.ionescu@arm.com>
-
- * opcodes/arm-dis.c (mve_opcodes): Enable VMOV imm to vec with
- cmode 1101.
- (is_mve_encoding_conflict): Update cmode conflict checks for
- MVE_VMVN_IMM.
-
-2019-11-12 Jan Beulich <jbeulich@suse.com>
-
- * i386-gen.c (operand_type_init): Remove OPERAND_TYPE_ESSEG
- entry.
- (operand_types): Remove EsSeg entry.
- (main): Replace stale use of OTMax.
- * i386-opc.h (IS_STRING_ES_OP0, IS_STRING_ES_OP1): Define.
- (struct i386_opcode_modifier): Expand isstring field to 2 bits.
- (EsSeg): Delete.
- (OTUnused): Comment out.
- (union i386_operand_type): Remove esseg field.
- * i386-opc.tbl (IsStringEsOp0, IsStringEsOp1): Define.
- (cmps, scmp, scas, ssca, cmpsd): Add IsStringEsOp0.
- (ins, movs, smov, movsd): Add IsStringEsOpOp1.
- (stos, ssto): Add IsStringEsOp0/IsStringEsOpOp1.
- * i386-init.h, i386-tbl.h: Re-generate.
-
-2019-11-12 Jan Beulich <jbeulich@suse.com>
-
- * i386-gen.c (operand_instances): Add RegB entry.
- * i386-opc.h (enum operand_instance): Add RegB.
- * i386-opc.tbl (RegC, RegD, RegB): Define.
- (Acc, ShiftCount, InOutPortReg): Adjust definitions.
- (monitor, mwait, invlpga, skinit, vmload, vmrun, vmsave, clzero,
- monitorx, mwaitx): Drop ImmExt and convert encodings
- accordingly.
- * i386-reg.tbl (ecx, rcx): Add Instance=RegC.
- (edx, rdx): Add Instance=RegD.
- (ebx, rbx): Add Instance=RegB.
- * i386-tbl.h: Re-generate.
-
-2019-11-12 Jan Beulich <jbeulich@suse.com>
-
- * i386-gen.c (operand_type_init): Adjust
- OPERAND_TYPE_INOUTPORTREG, OPERAND_TYPE_SHIFTCOUNT,
- OPERAND_TYPE_FLOATACC, OPERAND_TYPE_ACC8, OPERAND_TYPE_ACC16,
- OPERAND_TYPE_ACC32, and OPERAND_TYPE_ACC64 entries.
- (operand_instances): New.
- (operand_types): Drop InOutPortReg, ShiftCount, and Acc entries.
- (output_operand_type): New parameter "instance". Process it.
- (process_i386_operand_type): New local variable "instance".
- (main): Adjust static assertions.
- * i386-opc.h (INSTANCE_WIDTH): Define.
- (enum operand_instance): New.
- (Acc, InOutPortReg, ShiftCount): Replace by ClassInstance.
- (union i386_operand_type): Replace acc, inoutportreg, and
- shiftcount by instance.
- * i386-opc.tbl (Acc, InOutPortReg, ShiftCount): Define.
- * i386-reg.tbl (st, al, cl, ax, dx, eax, rax, xmm0, st(0)):
- Add Instance=.
- * i386-init.h, i386-tbl.h: Re-generate.
-
-2019-11-11 Jan Beulich <jbeulich@suse.com>
-
- * aarch64-tbl.h (aarch64_opcode_table): Switch SVE2's
- smaxp/sminp entries' "tied_operand" field to 2.
-
-2019-11-11 Jan Beulich <jbeulich@suse.com>
-
- * aarch64-opc.c (operand_general_constraint_met_p): Replace
- "index" local variable by that of the already existing "num".
-
-2019-11-08 H.J. Lu <hongjiu.lu@intel.com>
-
- PR gas/25167
- * i386-opc.tbl: Remove IgnoreSize from cmpsd and movsd.
- * i386-tbl.h: Regenerated.
-
-2019-11-08 Jan Beulich <jbeulich@suse.com>
-
- * i386-gen.c (operand_type_init): Add Class= to
- OPERAND_TYPE_REGMASK and OPERAND_TYPE_REGBND entries. Move up
- OPERAND_TYPE_REGBND entry.
- (operand_classes): Add RegMask and RegBND entries.
- (operand_types): Drop RegMask and RegBND entry.
- * i386-opc.h (enum operand_class): Add RegMask and RegBND.
- (RegMask, RegBND): Delete.
- (union i386_operand_type): Remove regmask and regbnd fields.
- * i386-opc.tbl (RegMask, RegBND): Define.
- * i386-reg.tbl: Replace RegMask by Class=RegMask and RegBND by
- Class=RegBND.
- * i386-init.h, i386-tbl.h: Re-generate.
-
-2019-11-08 Jan Beulich <jbeulich@suse.com>
-
- * i386-gen.c (operand_type_init): Add Class= to
- OPERAND_TYPE_REGMMX, OPERAND_TYPE_REGXMM, OPERAND_TYPE_REGYMM, and
- OPERAND_TYPE_REGZMM entries.
- (operand_classes): Add RegMMX and RegSIMD entries.
- (operand_types): Drop RegMMX and RegSIMD entries.
- * i386-opc.h (enum operand_class): Add RegMMX and RegSIMD.
- (RegMMX, RegSIMD): Delete.
- (union i386_operand_type): Remove regmmx and regsimd fields.
- * i386-opc.tbl (RegMMX): Define.
- (RegXMM, RegYMM, RegZMM): Add Class=.
- * i386-reg.tbl: Replace RegMMX by Class=RegMMX and RegSIMD by
- Class=RegSIMD.
- * i386-init.h, i386-tbl.h: Re-generate.
-
-2019-11-08 Jan Beulich <jbeulich@suse.com>
-
- * i386-gen.c (operand_type_init): Add Class= to
- OPERAND_TYPE_CONTROL, OPERAND_TYPE_TEST, and OPERAND_TYPE_DEBUG
- entries.
- (operand_classes): Add RegCR, RegDR, and RegTR entries.
- (operand_types): Drop Control, Debug, and Test entries.
- * i386-opc.h (enum operand_class): Add RegCR, RegDR, and RegTR.
- (Control, Debug, Test): Delete.
- (union i386_operand_type): Remove control, debug, and test
- fields.
- * i386-opc.tbl (Control, Debug, Test): Define.
- * i386-reg.tbl: Replace Control by Class=RegCR, Debug by
- Class=RegDR, and Test by Class=RegTR.
- * i386-init.h, i386-tbl.h: Re-generate.
-
-2019-11-08 Jan Beulich <jbeulich@suse.com>
-
- * i386-gen.c (operand_type_init): Add Class= to
- OPERAND_TYPE_SREG entry.
- (operand_classes): Add SReg entry.
- (operand_types): Drop SReg entry.
- * i386-opc.h (enum operand_class): Add SReg.
- (SReg): Delete.
- (union i386_operand_type): Remove sreg field.
- * i386-opc.tbl (SReg): Define.
- * i386-reg.tbl: Replace SReg by Class=SReg.
- * i386-init.h, i386-tbl.h: Re-generate.
-
-2019-11-08 Jan Beulich <jbeulich@suse.com>
-
- * i386-gen.c (operand_type_init): Add Class=. New
- OPERAND_TYPE_ANYIMM entry.
- (operand_classes): New.
- (operand_types): Drop Reg entry.
- (output_operand_type): New parameter "class". Process it.
- (process_i386_operand_type): New local variable "class".
- (main): Adjust static assertions.
- * i386-opc.h (CLASS_WIDTH): Define.
- (enum operand_class): New.
- (Reg): Replace by Class. Adjust comment.
- (union i386_operand_type): Replace reg by class.
- * i386-opc.tbl (Reg8, Reg16, Reg32, Reg64, FloatReg): Add
- Class=.
- * i386-reg.tbl: Replace Reg by Class=Reg.
- * i386-init.h: Re-generate.
-
-2019-11-07 Mihail Ionescu <mihail.ionescu@arm.com>
-
- * opcodes/aarch64-tbl.h (V8_6_INSN): New macro for v8.6 instructions.
- (aarch64_opcode_table): Add data gathering hint mnemonic.
- * opcodes/aarch64-dis-2.c: Account for new instruction.
-
-2019-11-07 Mihail Ionescu <mihail.ionescu@arm.com>
-
- * arm-dis.c (neon_opcodes): Add i8mm SIMD instructions.
-
-
-2019-11-07 Mihail Ionescu <mihail.ionescu@arm.com>
-
- * aarch64-tbl.h (aarch64_feature_i8mm_sve, aarch64_feature_f32mm_sve,
- aarch64_feature_f64mm_sve, aarch64_feature_i8mm, aarch64_feature_f32mm,
- aarch64_feature_f64mm): New feature sets.
- (INT8MATMUL_INSN, F64MATMUL_SVE_INSN, F64MATMUL_INSN,
- F32MATMUL_SVE_INSN, F32MATMUL_INSN): New macros to define matrix multiply
- instructions.
- (I8MM_SVE, F32MM_SVE, F64MM_SVE, I8MM, F32MM, F64MM): New feature set
- macros.
- (QL_MMLA64, OP_SVE_SBB): New qualifiers.
- (OP_SVE_QQQ): New qualifier.
- (INT8MATMUL_SVE_INSNC, F64MATMUL_SVE_INSNC,
- F32MATMUL_SVE_INSNC): New feature set for bfloat16 instructions to support
- the movprfx constraint.
- (aarch64_opcode_table): Support for SVE_ADDR_RI_S4x32.
- (aarch64_opcode_table): Define new instructions smmla,
- ummla, usmmla, usdot, sudot, fmmla, ld1rob, ld1roh, ld1row, ld1rod,
- uzip{1/2}, trn{1/2}.
- * aarch64-opc.c (operand_general_constraint_met_p): Handle
- AARCH64_OPND_SVE_ADDR_RI_S4x32.
- (aarch64_print_operand): Handle AARCH64_OPND_SVE_ADDR_RI_S4x32.
- * aarch64-dis-2.c (aarch64_opcode_lookup_1, aarch64_find_next_opcode):
- Account for new instructions.
- * opcodes/aarch64-asm-2.c (aarch64_insert_operand): Support the new
- S4x32 operand.
- * aarch64-opc-2.c (aarch64_operands): Support the new S4x32 operand.
-
-2019-11-07 Mihail Ionescu <mihail.ionescu@arm.com>
-2019-11-07 Matthew Malcomson <matthew.malcomson@arm.com>
-
- * arm-dis.c (select_arm_features): Update bfd_march_arm_8 with
- Armv8.6-A.
- (coprocessor_opcodes): Add bfloat16 vcvt{t,b}.
- (neon_opcodes): Add bfloat SIMD instructions.
- (print_insn_coprocessor): Add new control character %b to print
- condition code without checking cp_num.
- (print_insn_neon): Account for BFloat16 instructions that have no
- special top-byte handling.
-
-2019-11-07 Mihail Ionescu <mihail.ionescu@arm.com>
-2019-11-07 Matthew Malcomson <matthew.malcomson@arm.com>
-
- * arm-dis.c (print_insn_coprocessor,
- print_insn_generic_coprocessor): Create wrapper functions around
- the implementation of the print_insn_coprocessor control codes.
- (print_insn_coprocessor_1): Original print_insn_coprocessor
- function that now takes which array to look at as an argument.
- (print_insn_arm): Use both print_insn_coprocessor and
- print_insn_generic_coprocessor.
- (print_insn_thumb32): As above.
-
-2019-11-07 Mihail Ionescu <mihail.ionescu@arm.com>
-2019-11-07 Matthew Malcomson <matthew.malcomson@arm.com>
-
- * aarch64-asm.c (aarch64_ins_reglane): Use AARCH64_OPND_QLF_S_2H
- in reglane special case.
- * aarch64-dis-2.c (aarch64_opcode_lookup_1,
- aarch64_find_next_opcode): Account for new instructions.
- * aarch64-dis.c (aarch64_ext_reglane): Use AARCH64_OPND_QLF_S_2H
- in reglane special case.
- * aarch64-opc.c (struct operand_qualifier_data): Add data for
- new AARCH64_OPND_QLF_S_2H qualifier.
- * aarch64-tbl.h (QL_BFDOT QL_BFDOT64, QL_BFDOT64I, QL_BFMMLA2,
- QL_BFCVT64, QL_BFCVTN64, QL_BFCVTN2_64): New qualifiers.
- (aarch64_feature_bfloat16, aarch64_feature_bfloat16_sve): New feature
- sets.
- (BFLOAT_SVE, BFLOAT): New feature set macros.
- (BFLOAT_SVE_INSN, BFLOAT_INSN): New macros to define BFloat16
- instructions.
- (aarch64_opcode_table): Define new instructions bfdot,
- bfmmla, bfcvt, bfcvtnt, bfdot, bfdot, bfcvtn, bfmlal[b/t]
- bfcvtn2, bfcvt.
-
-2019-11-07 Mihail Ionescu <mihail.ionescu@arm.com>
-2019-11-07 Matthew Malcomson <matthew.malcomson@arm.com>
-
- * aarch64-tbl.h (ARMV8_6): New macro.
-
-2019-11-07 Jan Beulich <jbeulich@suse.com>
-
- * i386-dis.c (prefix_table): Add mcommit.
- (rm_table): Add rdpru.
- * i386-gen.c (cpu_flag_init): Adjust CPU_ZNVER2_FLAGS entry. Add
- CPU_RDPRU_FLAGS and CPU_MCOMMIT_FLAGS entries.
- (cpu_flags): Add CpuRDPRU and CpuMCOMMIT entries.
- * i386-opc.h (CpuRDPRU, CpuMCOMMIT): New.
- (union i386_cpu_flags): Add cpurdpru and cpumcommit fields.
- * i386-opc.tbl (mcommit, rdpru): New.
- * i386-init.h, i386-tbl.h: Re-generate.
-
-2019-11-07 Jan Beulich <jbeulich@suse.com>
-
- * i386-dis.c (OP_Mwait): Drop local variable "names", use
- "names32" instead.
- (OP_Monitor): Drop local variable "op1_names", re-purpose
- "names" for it instead, and replace former "names" uses by
- "names32" ones.
-
-2019-11-07 Jan Beulich <jbeulich@suse.com>
-
- PR/gas 25167
- * opcodes/i386-opc.tbl (movsd, cmpsd): Drop IgnoreSize from
- operand-less forms.
- * opcodes/i386-tbl.h: Re-generate.
-
-2019-11-05 Jan Beulich <jbeulich@suse.com>
-
- * i386-dis.c (OP_Mwaitx): Delete.
- (prefix_table): Use OP_Mwait for mwaitx entry.
- (OP_Mwait): Also handle mwaitx.
-
-2019-11-05 Jan Beulich <jbeulich@suse.com>
-
- * i386-dis.c (PREFIX_0F01_REG_7_MOD_3_RM_2,
- PREFIX_0F01_REG_7_MOD_3_RM_3): New.
- (prefix_table): Add respective entries.
- (rm_table): Link to those entries.
-
-2019-11-05 Jan Beulich <jbeulich@suse.com>
-
- * i386-dis.c (REG_0F1C_MOD_0): Rename to ...
- (REG_0F1C_P_0_MOD_0): ... this.
- (REG_0F1E_MOD_3): Rename to ...
- (REG_0F1E_P_1_MOD_3): ... this.
- (RM_0F01_REG_5): Rename to ...
- (RM_0F01_REG_5_MOD_3): ... this.
- (RM_0F01_REG_7): Rename to ...
- (RM_0F01_REG_7_MOD_3): ... this.
- (RM_0F1E_MOD_3_REG_7): Rename to ...
- (RM_0F1E_P_1_MOD_3_REG_7): ... this.
- (RM_0FAE_REG_6): Rename to ...
- (RM_0FAE_REG_6_MOD_3_P_0): ... this.
- (RM_0FAE_REG_7): Rename to ...
- (RM_0FAE_REG_7_MOD_3): ... this.
- (PREFIX_MOD_0_0F01_REG_5): Rename to ...
- (PREFIX_0F01_REG_5_MOD_0): ... this.
- (PREFIX_MOD_3_0F01_REG_5_RM_0): Rename to ...
- (PREFIX_0F01_REG_5_MOD_3_RM_0): ... this.
- (PREFIX_MOD_3_0F01_REG_5_RM_2): Rename to ...
- (PREFIX_0F01_REG_5_MOD_3_RM_2): ... this.
- (PREFIX_0FAE_REG_0): Rename to ...
- (PREFIX_0FAE_REG_0_MOD_3): ... this.
- (PREFIX_0FAE_REG_1): Rename to ...
- (PREFIX_0FAE_REG_1_MOD_3): ... this.
- (PREFIX_0FAE_REG_2): Rename to ...
- (PREFIX_0FAE_REG_2_MOD_3): ... this.
- (PREFIX_0FAE_REG_3): Rename to ...
- (PREFIX_0FAE_REG_3_MOD_3): ... this.
- (PREFIX_MOD_0_0FAE_REG_4): Rename to ...
- (PREFIX_0FAE_REG_4_MOD_0): ... this.
- (PREFIX_MOD_3_0FAE_REG_4): Rename to ...
- (PREFIX_0FAE_REG_4_MOD_3): ... this.
- (PREFIX_MOD_0_0FAE_REG_5): Rename to ...
- (PREFIX_0FAE_REG_5_MOD_0): ... this.
- (PREFIX_MOD_3_0FAE_REG_5): Rename to ...
- (PREFIX_0FAE_REG_5_MOD_3): ... this.
- (PREFIX_MOD_0_0FAE_REG_6): Rename to ...
- (PREFIX_0FAE_REG_6_MOD_0): ... this.
- (PREFIX_MOD_1_0FAE_REG_6): Rename to ...
- (PREFIX_0FAE_REG_6_MOD_3): ... this.
- (PREFIX_0FAE_REG_7): Rename to ...
- (PREFIX_0FAE_REG_7_MOD_0): ... this.
- (PREFIX_MOD_0_0FC3): Rename to ...
- (PREFIX_0FC3_MOD_0): ... this.
- (PREFIX_MOD_0_0FC7_REG_6): Rename to ...
- (PREFIX_0FC7_REG_6_MOD_0): ... this.
- (PREFIX_MOD_3_0FC7_REG_6): Rename to ...
- (PREFIX_0FC7_REG_6_MOD_3): ... this.
- (PREFIX_MOD_3_0FC7_REG_7): Rename to ...
- (PREFIX_0FC7_REG_7_MOD_3): ... this.
- (reg_table, prefix_table, mod_table, rm_table): Adjust
- accordingly.
-
-2019-11-04 Nick Clifton <nickc@redhat.com>
-
- * v850-dis.c (get_v850_sreg_name): New function. Returns the name
- of a v850 system register. Move the v850_sreg_names array into
- this function.
- (get_v850_reg_name): Likewise for ordinary register names.
- (get_v850_vreg_name): Likewise for vector register names.
- (get_v850_cc_name): Likewise for condition codes.
- * get_v850_float_cc_name): Likewise for floating point condition
- codes.
- (get_v850_cacheop_name): Likewise for cache-ops.
- (get_v850_prefop_name): Likewise for pref-ops.
- (disassemble): Use the new accessor functions.
-
-2019-10-30 Delia Burduv <delia.burduv@arm.com>
-
- * aarch64-opc.c (print_immediate_offset_address): Don't print the
- immediate for the writeback form of ldraa/ldrab if it is 0.
- * aarch64-tbl.h: Updated the documentation for ADDR_SIMM10.
- * aarch64-opc-2.c: Regenerated.
-
-2019-10-30 Jan Beulich <jbeulich@suse.com>
-
- * i386-gen.c (operand_type_shorthands): Delete.
- (operand_type_init): Expand previous shorthands.
- (set_bitfield_from_shorthand): Rename back to ...
- (set_bitfield_from_cpu_flag_init): ... this. Drop processing
- of operand_type_init[].
- (set_bitfield): Adjust call to the above function.
- * i386-opc.tbl (Reg8, Reg16, Reg32, Reg64, FloatAcc, FloatReg,
- RegXMM, RegYMM, RegZMM): Define.
- * i386-reg.tbl: Expand prior shorthands.
-
-2019-10-30 Jan Beulich <jbeulich@suse.com>
-
- * i386-gen.c (output_i386_opcode): Change order of fields
- emitted to output.
- * i386-opc.h (struct insn_template): Move operands field.
- Convert extension_opcode field to unsigned short.
- * i386-tbl.h: Re-generate.
-
-2019-10-30 Jan Beulich <jbeulich@suse.com>
-
- * i386-gen.c (process_i386_opcode_modifier): Report bogus uses
- of W.
- * i386-opc.h (W): Extend comment.
- * i386-opc.tbl (mov, movabs, movq): Drop W and adjust opcodes of
- general purpose variants not allowing for byte operands.
- * i386-tbl.h: Re-generate.
-
-2019-10-29 Nick Clifton <nickc@redhat.com>
-
- * tic30-dis.c (print_branch): Correct size of operand array.
-
-2019-10-29 Nick Clifton <nickc@redhat.com>
-
- * d30v-dis.c (print_insn): Check that operand index is valid
- before attempting to access the operands array.
-
-2019-10-29 Nick Clifton <nickc@redhat.com>
-
- * ia64-opc.c (locate_opcode_ent): Prevent a negative shift when
- locating the bit to be tested.
-
-2019-10-29 Nick Clifton <nickc@redhat.com>
-
- * s12z-dis.c (opr_emit_disassembly): Check for illegal register
- values.
- (shift_size_table): Use a fixed size defined as S12Z_N_SIZES.
- (print_insn_s12z): Check for illegal size values.
-
-2019-10-28 Nick Clifton <nickc@redhat.com>
-
- * csky-dis.c (csky_chars_to_number): Check for a negative
- count. Use an unsigned integer to construct the return value.
-
-2019-10-28 Nick Clifton <nickc@redhat.com>
-
- * tic30-dis.c (OPERAND_BUFFER_LEN): Define. Use as length of
- operand buffer. Set value to 15 not 13.
- (get_register_operand): Use OPERAND_BUFFER_LEN.
- (get_indirect_operand): Likewise.
- (print_two_operand): Likewise.
- (print_three_operand): Likewise.
- (print_oar_insn): Likewise.
-
-2019-10-28 Nick Clifton <nickc@redhat.com>
-
- * ns32k-dis.c (bit_extract): Add sanitiy check of parameters.
- (bit_extract_simple): Likewise.
- (bit_copy): Likewise.
- (pirnt_insn_ns32k): Ensure that uninitialised elements in the
- index_offset array are not accessed.
-
-2019-10-28 Nick Clifton <nickc@redhat.com>
-
- * xgate-dis.c (print_insn): Fix decoding of the XGATE_OP_DYA
- operand.
-
-2019-10-25 Nick Clifton <nickc@redhat.com>
-
- * rx-dis.c (print_insn_rx): Use parenthesis to ensure correct
- access to opcodes.op array element.
-
-2019-10-23 Nick Clifton <nickc@redhat.com>
-
- * rx-dis.c (get_register_name): Fix spelling typo in error
- message.
- (get_condition_name, get_flag_name, get_double_register_name)
- (get_double_register_high_name, get_double_register_low_name)
- (get_double_control_register_name, get_double_condition_name)
- (get_opsize_name, get_size_name): Likewise.
-
-2019-10-22 Nick Clifton <nickc@redhat.com>
-
- * rx-dis.c (get_size_name): New function. Provides safe
- access to name array.
- (get_opsize_name): Likewise.
- (print_insn_rx): Use the accessor functions.
-
-2019-10-16 Nick Clifton <nickc@redhat.com>
-
- * rx-dis.c (get_register_name): New function. Provides safe
- access to name array.
- (get_condition_name, get_flag_name, get_double_register_name)
- (get_double_register_high_name, get_double_register_low_name)
- (get_double_control_register_name, get_double_condition_name):
- Likewise.
- (print_insn_rx): Use the accessor functions.
-
-2019-10-09 Nick Clifton <nickc@redhat.com>
-
- PR 25041
- * avr-dis.c (avr_operand): Fix construction of address for lds/sts
- instructions.
-
-2019-10-07 Jan Beulich <jbeulich@suse.com>
-
- * opcodes/i386-opc.tbl (movsd): Add Dword and IgnoreSize.
- (cmpsd): Likewise. Move EsSeg to other operand.
- * opcodes/i386-tbl.h: Re-generate.
-
-2019-09-23 Alan Modra <amodra@gmail.com>
-
- * m68k-dis.c: Include cpu-m68k.h
-
-2019-09-23 Alan Modra <amodra@gmail.com>
-
- * mips-dis.c: Include elfxx-mips.h. Move "elf-bfd.h" and
- "elf/mips.h" earlier.
-
-2018-09-20 Jan Beulich <jbeulich@suse.com>
-
- PR gas/25012
- * i386-opc.tbl (push, pop): Re-instate distinct Cpu64 templates
- with SReg operand.
- * i386-tbl.h: Re-generate.
-
-2019-09-18 Alan Modra <amodra@gmail.com>
-
- * arc-ext.c: Update throughout for bfd section macro changes.
-
-2019-09-18 Simon Marchi <simon.marchi@polymtl.ca>
-
- * Makefile.in: Re-generate.
- * configure: Re-generate.
-
-2019-09-17 Maxim Blinov <maxim.blinov@embecosm.com>
-
- * riscv-opc.c (riscv_opcodes): Change subset field
- to insn_class field for all instructions.
- (riscv_insn_types): Likewise.
-
-2019-09-16 Phil Blundell <pb@pbcl.net>
-
- * configure: Regenerated.
-
-2019-09-10 Miod Vallat <miod@online.fr>
-
- PR 24982
- * m68k-opc.c: Correct aliases for tdivsl and tdivul.
-
-2019-09-09 Phil Blundell <pb@pbcl.net>
-
- binutils 2.33 branch created.
-
-2019-09-03 Nick Clifton <nickc@redhat.com>
-
- PR 24961
- * tic30-dis.c (get_indirect_operand): Check for bufcnt being
- greater than zero before indexing via (bufcnt -1).
-
-2019-09-03 Nick Clifton <nickc@redhat.com>
-
- PR 24958
- * mmix-dis.c (MAX_REG_NAME_LEN): Define.
- (MAX_SPEC_REG_NAME_LEN): Define.
- (struct mmix_dis_info): Use defined constants for array lengths.
- (get_reg_name): New function.
- (get_sprec_reg_name): New function.
- (print_insn_mmix): Use new functions.
-
-2019-08-27 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
-
- * arm-dis.c (mve_opcodes): Add entry for MVE_VMOV_VEC_TO_VEC.
- (is_mve_undefined): Add case for MVE_VMOV_VEC_TO_VEC.
- (print_insn_mve): Add condition to check Qm==Qn of VORR instruction.
-
-2019-08-22 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
-
- * aarch64-opc.c (aarch64_sys_regs): Update encoding of tfsre0_el1,
- tfsr_el1, tfsr_el2, tfsr_el3, tfsr_el12.
- (aarch64_sys_reg_supported_p): Update checks for the above.
-
-2019-08-12 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
-
- * arm-dis.c (struct mopcode32 mve_opcodes): Modify the mask for
- cases MVE_SQRSHRL and MVE_UQRSHLL.
- (print_insn_mve): Add case for specifier 'k' to check
- specific bit of the instruction.
-
-2019-08-07 Phillipe Antoine <p.antoine@catenacyber.fr>
-
- PR 24854
- * arc-dis.c (arc_insn_length): Return 0 rather than aborting when
- encountering an unknown machine type.
- (print_insn_arc): Handle arc_insn_length returning 0. In error
- cases return -1 rather than calling abort.
-
-2019-08-07 Jan Beulich <jbeulich@suse.com>
-
- * i386-opc.tbl (fld, fstp): Drop FloatMF from extended forms.
- (fldcw, fnstcw, fstcw, fnstsw, fstsw): Replace FloatMF by
- IgnoreSize.
- * i386-tbl.h: Re-generate.
-
-2019-08-05 Barnaby Wilks <barnaby.wilks@arm.com>
-
- * arm-dis.c: Only accept signed variants of VQ(R)DMLAH and VQ(R)DMLASH
- instructions.
-
-2019-07-30 Mel Chen <mel.chen@sifive.com>
-
- * riscv-opc.c (riscv_opcodes): Set frsr, fssr, frcsr, fscsr, frrm,
- fsrm, fsrmi, frflags, fsflags, fsflagsi to alias instructions.
-
- * riscv-opc.c (riscv_opcodes): Adjust order of frsr, frcsr, fssr,
- fscsr.
-
-2019-07-24 Claudiu Zissulescu <claziss@synopsys.com>
-
- * arc-dis.c (skip_this_opcode): Check also for 0x07 major opcodes,
- and MPY class instructions.
- (parse_option): Add nps400 option.
- (print_arc_disassembler_options): Add nps400 info.
-
-2019-07-24 Claudiu Zissulescu <claziss@synopsys.com>
-
- * arc-ext-tbl.h (bspeek): Remove it, added to main table.
- (bspop): Likewise.
- (modapp): Likewise.
- * arc-opc.c (RAD_CHK): Add.
- * arc-tbl.h: Regenerate.
-
-2019-07-23 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
-
- * aarch64-opc.c (aarch64_sys_regs): Add gmid_el1 entry.
- (aarch64_sys_reg_supported_p): Handle gmid_el1 encoding.
-
-2019-07-22 Barnaby Wilks <barnaby.wilks@arm.com>
-
- * arm-dis.c (is_mve_unpredictable): Stop marking some MVE
- instructions as UNPREDICTABLE.
-
-2019-07-19 Jose E. Marchesi <jose.marchesi@oracle.com>
-
- * bpf-desc.c: Regenerated.
-
-2019-07-17 Jan Beulich <jbeulich@suse.com>
-
- * i386-gen.c (static_assert): Define.
- (main): Use it.
- * i386-opc.h (Opcode_Modifier_Max): Rename to ...
- (Opcode_Modifier_Num): ... this.
- (Mem): Delete.
-
-2019-07-16 Jan Beulich <jbeulich@suse.com>
-
- * i386-gen.c (operand_types): Move RegMem ...
- (opcode_modifiers): ... here.
- * i386-opc.h (RegMem): Move to opcode modifer enum.
- (union i386_operand_type): Move regmem field ...
- (struct i386_opcode_modifier): ... here.
- * i386-opc.tbl (RegMem): Define.
- (mov, movq): Move RegMem on segment, control, debug, and test
- register flavors.
- (pextrb): Move RegMem on register only flavors. Add IgnoreSize
- to non-SSE2AVX flavor.
- (extractps, pextrw, vcvtps2ph, vextractps, vpextrb, vpextrw):
- Move RegMem on register only flavors. Drop IgnoreSize from
- legacy encoding flavors.
- (movss, movsd, vmovss, vmovsd): Drop RegMem from register only
- flavors.
- (vpinsrb, vpinsrw): Drop IgnoreSize where still present on
- register only flavors.
- (vmovd): Move RegMem and drop IgnoreSize on register only
- flavor. Change opcode and operand order to store form.
- * opcodes/i386-init.h, i386-tbl.h: Re-generate.
-
-2019-07-16 Jan Beulich <jbeulich@suse.com>
-
- * i386-gen.c (operand_type_init, operand_types): Replace SReg
- entries.
- * i386-opc.h (SReg2, SReg3): Replace by ...
- (SReg): ... this.
- (union i386_operand_type): Replace sreg fields.
- * i386-opc.tbl (mov, ): Use SReg.
- (push, pop): Likewies. Drop i386 and x86-64 specific segment
- register flavors.
- * i386-reg.tbl (cs, ds, es, fs, gs, ss, flat): Use SReg.
- * opcodes/i386-init.h, i386-tbl.h: Re-generate.
-
-2019-07-15 Jose E. Marchesi <jose.marchesi@oracle.com>
-
- * bpf-desc.c: Regenerate.
- * bpf-opc.c: Likewise.
- * bpf-opc.h: Likewise.
-
-2019-07-14 Jose E. Marchesi <jose.marchesi@oracle.com>
-
- * bpf-desc.c: Regenerate.
- * bpf-opc.c: Likewise.
-
-2019-07-10 Hans-Peter Nilsson <hp@bitrange.com>
-
- * arm-dis.c (print_insn_coprocessor): Rename index to
- index_operand.
-
-2019-07-05 Kito Cheng <kito.cheng@sifive.com>
-
- * riscv-opc.c (riscv_insn_types): Add r4 type.
-
- * riscv-opc.c (riscv_insn_types): Add b and j type.
-
- * opcodes/riscv-opc.c (riscv_insn_types): Remove incorrect
- format for sb type and correct s type.
-
-2019-07-02 Richard Sandiford <richard.sandiford@arm.com>
-
- * aarch64-tbl.h (aarch64_opcode): Set C_SCAN_MOVPRFX for the
- SVE FMOV alias of FCPY.
-
-2019-07-02 Richard Sandiford <richard.sandiford@arm.com>
-
- * aarch64-tbl.h (aarch64_opcode_table): Add C_MAX_ELEM flags
- to SVE fcvtzs, fcvtzu, scvtf and ucvtf entries.
-
-2019-07-02 Richard Sandiford <richard.sandiford@arm.com>
-
- * aarch64-opc.c (verify_constraints): Skip GPRs when scanning the
- registers in an instruction prefixed by MOVPRFX.
-
-2019-07-01 Matthew Malcomson <matthew.malcomson@arm.com>
-
- * aarch64-asm.c (aarch64_encode_variant_using_iclass): Use new
- sve_size_13 icode to account for variant behaviour of
- pmull{t,b}.
- * aarch64-dis-2.c: Regenerate.
- * aarch64-dis.c (aarch64_decode_variant_using_iclass): Use new
- sve_size_13 icode to account for variant behaviour of
- pmull{t,b}.
- * aarch64-tbl.h (OP_SVE_VVV_HD_BS): Add new qualifier.
- (OP_SVE_VVV_Q_D): Add new qualifier.
- (OP_SVE_VVV_QHD_DBS): Remove now unused qualifier.
- (struct aarch64_opcode): Split pmull{t,b} into those requiring
- AES and those not.
-
-2019-07-01 Jan Beulich <jbeulich@suse.com>
-
- * opcodes/i386-gen.c (operand_type_init): Remove
- OPERAND_TYPE_VEC_IMM4 entry.
- (operand_types): Remove Vec_Imm4.
- * opcodes/i386-opc.h (Vec_Imm4): Delete.
- (union i386_operand_type): Remove vec_imm4.
- * i386-opc.tbl (vpermil2pd, vpermil2ps): Remove Vec_Imm4.
- * opcodes/i386-init.h, i386-tbl.h: Re-generate.
-
-2019-07-01 Jan Beulich <jbeulich@suse.com>
-
- * i386-opc.tbl (lfence, mfence, sfence, monitor, mwait, vmcall,
- vmlaunch, vmresume, vmxoff, vmfunc, xgetbv, xsetbv, swapgs,
- rdtscp, clgi, invlpga, skinit, stgi, vmload, vmmcall, vmrun,
- vmsave, montmul, xsha1, xsha256, xstorerng, xcryptecb,
- xcryptcbc, xcryptctr, xcryptcfb, xcryptofb, xstore, clac, stac,
- monitorx, mwaitx): Drop ImmExt from operand-less forms.
- * i386-tbl.h: Re-generate.
-
-2019-07-01 Jan Beulich <jbeulich@suse.com>
-
- * i386-opc.tbl (and, or): Add Optimize to forms allowing two
- register operands.
- * i386-tbl.h: Re-generate.
-
-2019-07-01 Jan Beulich <jbeulich@suse.com>
-
- * i386-opc.tbl (C): New.
- (paddb, paddw, paddd, paddq, paddsb, paddsw, paddusb, paddusw,
- pand, pcmpeqb, pcmpeqw, pcmpeqd, pmaddwd, pmulhw, pmullw,
- por, pxor, andps, cmpeqps, cmpeqss, cmpneqps, cmpneqss,
- cmpordps, cmpordss, cmpunordps, cmpunordss, orps, pavgb, pavgw,
- pmaxsw, pmaxub, pminsw, pminub, pmulhuw, xorps, andpd, cmpeqpd,
- cmpeqsd, cmpneqpd, cmpneqsd, cmpordpd, cmpordsd, cmpunordpd,
- cmpunordsd, orpd, xorpd, pmuludq, vandpd, vandps, vcmpeq_ospd,
- vcmpeq_osps, vcmpeq_ossd, vcmpeq_osss, vcmpeqpd, vcmpeqps,
- vcmpeqsd, vcmpeqss, vcmpeq_uqpd, vcmpeq_uqps, vcmpeq_uqsd,
- vcmpeq_uqss, vcmpeq_uspd, vcmpeq_usps, vcmpeq_ussd,
- vcmpeq_usss, vcmpfalse_ospd, vcmpfalse_osps, vcmpfalse_ossd,
- vcmpfalse_osss, vcmpfalsepd, vcmpfalseps, vcmpfalsesd,
- vcmpfalsess, vcmpneq_oqpd, vcmpneq_oqps, vcmpneq_oqsd,
- vcmpneq_oqss, vcmpneq_ospd, vcmpneq_osps, vcmpneq_ossd,
- vcmpneq_osss, vcmpneqpd, vcmpneqps, vcmpneqsd, vcmpneqss,
- vcmpneq_uspd, vcmpneq_usps, vcmpneq_ussd, vcmpneq_usss,
- vcmpordpd, vcmpordps, vcmpordsd, vcmpord_spd, vcmpord_sps,
- vcmpordss, vcmpord_ssd, vcmpord_sss, vcmptruepd, vcmptrueps,
- vcmptruesd, vcmptruess, vcmptrue_uspd, vcmptrue_usps,
- vcmptrue_ussd, vcmptrue_usss, vcmpunordpd, vcmpunordps,
- vcmpunordsd, vcmpunord_spd, vcmpunord_sps, vcmpunordss,
- vcmpunord_ssd, vcmpunord_sss, vorpd, vorps, vpaddsb, vpaddsw,
- vpaddb, vpaddd, vpaddq, vpaddw, vpaddusb, vpaddusw, vpand,
- vpavgb, vpavgw, vpcmpeqb, vpcmpeqd, vpcmpeqw, vpmaddwd,
- vpmaxsw, vpmaxub, vpminsw, vpminub, vpmulhuw, vpmulhw, vpmullw,
- vpmuludq, vpor, vpxor, vxorpd, vxorps): Add C to VEX-encoded
- flavors.
- * i386-tbl.h: Re-generate.
-
-2019-07-01 Jan Beulich <jbeulich@suse.com>
-
- * i386-opc.tbl (and, or): Add Optimize to forms allowing two
- register operands.
- * i386-tbl.h: Re-generate.
-
-2019-07-01 Jan Beulich <jbeulich@suse.com>
-
- * i386-dis-evex-prefix.h: Use PCLMUL for vpclmulqdq.
- * i386-opc.tbl (vpclmullqlqdq, vpclmulhqlqdq, vpclmullqhqdq,
- vpclmulhqhqdq): Add CpuVPCLMULQDQ flavors.
- * i386-tbl.h: Re-generate.
-
-2019-07-01 Jan Beulich <jbeulich@suse.com>
-
- * i386-opc.tbl (vextractps, vpextrw, vpinsrw): Remove
- Disp8MemShift from register only templates.
- * i386-tbl.h: Re-generate.
-
-2019-07-01 Jan Beulich <jbeulich@suse.com>
-
- * i386-dis.c (EXdScalarS, MOD_EVEX_0F10_PREFIX_1,
- MOD_EVEX_0F10_PREFIX_3, MOD_EVEX_0F11_PREFIX_1,
- MOD_EVEX_0F11_PREFIX_3, EVEX_W_0F10_P_1_M_0,
- EVEX_W_0F10_P_1_M_1, EVEX_W_0F10_P_3_M_0, EVEX_W_0F10_P_3_M_1,
- EVEX_W_0F11_P_1_M_0, EVEX_W_0F11_P_1_M_1, EVEX_W_0F11_P_3_M_0,
- EVEX_W_0F11_P_3_M_1): Delete.
- (EVEX_W_0F10_P_1, EVEX_W_0F10_P_3, EVEX_W_0F11_P_1,
- EVEX_W_0F11_P_3): New.
- * i386-dis-evex-mod.h: Remove MOD_EVEX_0F10_PREFIX_1,
- MOD_EVEX_0F10_PREFIX_3, MOD_EVEX_0F11_PREFIX_1, and
- MOD_EVEX_0F11_PREFIX_3 table entries.
- * i386-dis-evex-prefix.h: Adjust PREFIX_EVEX_0F10 and
- PREFIX_EVEX_0F11 table entries.
- * i386-dis-evex-w.h: Replace EVEX_W_0F10_P_1_M_{0,1},
- EVEX_W_0F10_P_3_M_{0,1}, EVEX_W_0F11_P_1_M_{0,1}, and
- EVEX_W_0F11_P_3_M_{0,1} table entries.
-
-2019-07-01 Jan Beulich <jbeulich@suse.com>
-
- * i386-dis.c (EXdVex, EXdVexS, EXqVex, EXqVexS, XMVex):
- Delete.
-
-2019-06-27 H.J. Lu <hongjiu.lu@intel.com>
-
- PR binutils/24719
- * i386-dis-evex-len.h: Add EVEX_LEN_0F38C6_REG_1_PREFIX_2,
- EVEX_LEN_0F38C6_REG_2_PREFIX_2, EVEX_LEN_0F38C6_REG_5_PREFIX_2,
- EVEX_LEN_0F38C6_REG_6_PREFIX_2, EVEX_LEN_0F38C7_R_1_P_2_W_0,
- EVEX_LEN_0F38C7_R_1_P_2_W_1, EVEX_LEN_0F38C7_R_2_P_2_W_0,
- EVEX_LEN_0F38C7_R_2_P_2_W_1, EVEX_LEN_0F38C7_R_5_P_2_W_0,
- EVEX_LEN_0F38C7_R_5_P_2_W_1, EVEX_LEN_0F38C7_R_6_P_2_W_0 and
- EVEX_LEN_0F38C7_R_6_P_2_W_1.
- * i386-dis-evex-prefix.h: Update PREFIX_EVEX_0F38C6_REG_1,
- PREFIX_EVEX_0F38C6_REG_2, PREFIX_EVEX_0F38C6_REG_5 and
- PREFIX_EVEX_0F38C6_REG_6 entries.
- * i386-dis-evex-w.h: Update EVEX_W_0F38C7_R_1_P_2,
- EVEX_W_0F38C7_R_2_P_2, EVEX_W_0F38C7_R_5_P_2 and
- EVEX_W_0F38C7_R_6_P_2 entries.
- * i386-dis.c: Add EVEX_LEN_0F38C6_REG_1_PREFIX_2,
- EVEX_LEN_0F38C6_REG_2_PREFIX_2, EVEX_LEN_0F38C6_REG_5_PREFIX_2,
- EVEX_LEN_0F38C6_REG_6_PREFIX_2, EVEX_LEN_0F38C7_R_1_P_2_W_0,
- EVEX_LEN_0F38C7_R_1_P_2_W_1, EVEX_LEN_0F38C7_R_2_P_2_W_0,
- EVEX_LEN_0F38C7_R_2_P_2_W_1, EVEX_LEN_0F38C7_R_5_P_2_W_0,
- EVEX_LEN_0F38C7_R_5_P_2_W_1, EVEX_LEN_0F38C7_R_6_P_2_W_0 and
- EVEX_LEN_0F38C7_R_6_P_2_W_1 enums.
-
-2019-06-27 Jan Beulich <jbeulich@suse.com>
-
- * i386-dis.c (VEX_LEN_0F2A_P_1, VEX_LEN_0F2A_P_3,
- VEX_LEN_0F2C_P_1, VEX_LEN_0F2C_P_3, VEX_LEN_0F2D_P_1,
- VEX_LEN_0F2D_P_3): Delete.
- (vex_len_table): Move vcvtsi2ss, vcvtsi2sd, vcvttss2si,
- vcvttsd2si, vcvtss2si, and vcvtsd2si leaf entries ...
- (prefix_table): ... here.
-
-2019-06-27 Jan Beulich <jbeulich@suse.com>
-
- * i386-dis.c (Iq): Delete.
- (Id): New.
- (reg_table): Use it for lwpins, lwpval, and bextr. Use Edq for
- TBM insns.
- (vex_len_table): Use Edq for vcvtsi2ss, vcvtsi2sd. Use Gdq for
- vcvttss2si, vcvttsd2si, vcvtss2si, and vcvtsd2si.
- (OP_E_memory): Also honor needindex when deciding whether an
- address size prefix needs printing.
- (OP_I): Remove handling of q_mode. Add handling of d_mode.
-
-2019-06-26 Jim Wilson <jimw@sifive.com>
-
- PR binutils/24739
- * riscv-dis.c (riscv_disasemble_insn): Set info->endian_code.
- Set info->display_endian to info->endian_code.
-
-2019-06-25 Jan Beulich <jbeulich@suse.com>
-
- * i386-gen.c (operand_type_init): Correct OPERAND_TYPE_DEBUG
- entry. Drop OPERAND_TYPE_ACC entry. Add OPERAND_TYPE_ACC8 and
- OPERAND_TYPE_ACC16 entries. Adjust OPERAND_TYPE_ACC32 and
- OPERAND_TYPE_ACC64 entries.
- * i386-init.h: Re-generate.
-
-2019-06-25 Jan Beulich <jbeulich@suse.com>
-
- * i386-dis.c (Edqa, dqa_mode, EVEX_W_0F2A_P_1, EVEX_W_0F7B_P_1):
- Delete.
- (intel_operand_size, OP_E_register, OP_E_memory): Drop handling
- of dqa_mode.
- * i386-dis-evex-prefix.h: Move vcvtsi2ss and vcvtusi2ss leaf
- entries here.
- * i386-dis-evex-w.h: Drop EVEX_W_0F2A_P_1 and EVEX_W_0F7B_P_1
- entries. Use Edq for vcvtsi2sd and vcvtusi2sd.
-
-2019-06-25 Jan Beulich <jbeulich@suse.com>
-
- * i386-dis.c (OP_I64): Forword more cases to OP_I(). Drop local
- variables.
-
-2019-06-25 Jan Beulich <jbeulich@suse.com>
-
- * i386-dis.c (prefix_table): Use Edq for cvtsi2ss and cvtsi2sd.
- Use Gdq for cvttss2si, cvttsd2si, cvtss2si, and cvtsd2si, and
- movnti.
- * i386-opc.tbl (movnti): Add IgnoreSize.
- * i386-tbl.h: Re-generate.
-
-2019-06-25 Jan Beulich <jbeulich@suse.com>
-
- * i386-opc.tbl (and): Mark Imm8S form for optimization.