gdb: add target_ops::supports_displaced_step

[deliverable/binutils-gdb.git] / opcodes / aarch64-dis.c

diff --git a/opcodes/aarch64-dis.c b/opcodes/aarch64-dis.c
index 844c6ab68b2bfe8831478a9211a9da614f9e11d9..6567880efbaaeea5e1f2aa026df99059e9bb7471 100644 (file)
--- a/opcodes/aarch64-dis.c
+++ b/opcodes/aarch64-dis.c
@@ -1,5 +1,5 @@
 /* aarch64-dis.c -- AArch64 disassembler.
 /* aarch64-dis.c -- AArch64 disassembler.

-   Copyright (C) 2009-2019 Free Software Foundation, Inc.
+   Copyright (C) 2009-2020 Free Software Foundation, Inc.

    Contributed by ARM Ltd.
 
    This file is part of the GNU opcodes library.
    Contributed by ARM Ltd.
 
    This file is part of the GNU opcodes library.


@@ -178,18 +178,15 @@ extract_all_fields (const aarch64_operand *self, aarch64_insn code)
 }
 
 /* Sign-extend bit I of VALUE.  */
 }
 
 /* Sign-extend bit I of VALUE.  */

-static inline int32_t
+static inline uint64_t

 sign_extend (aarch64_insn value, unsigned i)
 {
 sign_extend (aarch64_insn value, unsigned i)
 {

-  uint32_t ret = value;
+  uint64_t ret, sign;

 
   assert (i < 32);
 
   assert (i < 32);

-  if ((value >> i) & 0x1)
-    {
-      uint32_t val = (uint32_t)(-1) << i;
-      ret = ret | val;
-    }
-  return (int32_t) ret;
+  ret = value;
+  sign = (uint64_t) 1 << i;
+  return ((ret & (sign + sign - 1)) ^ sign) - sign;

 }
 
 /* N.B. the following inline helpfer functions create a dependency on the
 }
 
 /* N.B. the following inline helpfer functions create a dependency on the


@@ -254,6 +251,16 @@ get_expected_qualifier (const aarch64_inst *inst, int i)
 
 /* Operand extractors.  */
 
 
 /* Operand extractors.  */
 

+bfd_boolean
+aarch64_ext_none (const aarch64_operand *self ATTRIBUTE_UNUSED,
+                 aarch64_opnd_info *info ATTRIBUTE_UNUSED,
+                 const aarch64_insn code ATTRIBUTE_UNUSED,
+                 const aarch64_inst *inst ATTRIBUTE_UNUSED,
+                 aarch64_operand_error *errors ATTRIBUTE_UNUSED)
+{
+  return TRUE;
+}
+

 bfd_boolean
 aarch64_ext_regno (const aarch64_operand *self, aarch64_opnd_info *info,
                   const aarch64_insn code,
 bfd_boolean
 aarch64_ext_regno (const aarch64_operand *self, aarch64_opnd_info *info,
                   const aarch64_insn code,


@@ -348,6 +355,7 @@ aarch64_ext_reglane (const aarch64_operand *self, aarch64_opnd_info *info,
       switch (info->qualifier)
        {
        case AARCH64_OPND_QLF_S_4B:
       switch (info->qualifier)
        {
        case AARCH64_OPND_QLF_S_4B:

+       case AARCH64_OPND_QLF_S_2H:

          /* L:H */
          info->reglane.index = extract_fields (code, 0, 2, FLD_H, FLD_L);
          info->reglane.regno &= 0x1f;
          /* L:H */
          info->reglane.index = extract_fields (code, 0, 2, FLD_H, FLD_L);
          info->reglane.regno &= 0x1f;


@@ -657,7 +665,7 @@ aarch64_ext_imm (const aarch64_operand *self, aarch64_opnd_info *info,
                 const aarch64_inst *inst ATTRIBUTE_UNUSED,
                 aarch64_operand_error *errors ATTRIBUTE_UNUSED)
 {
                 const aarch64_inst *inst ATTRIBUTE_UNUSED,
                 aarch64_operand_error *errors ATTRIBUTE_UNUSED)
 {

-  int64_t imm;
+  uint64_t imm;

 
   imm = extract_all_fields (self, code);
 
 
   imm = extract_all_fields (self, code);
 


@@ -2806,10 +2814,15 @@ aarch64_decode_variant_using_iclass (aarch64_inst *inst)
       variant = i - 1;
       break;
 
       variant = i - 1;
       break;
 

+    case sve_size_bh:

     case sve_size_sd:
       variant = extract_field (FLD_SVE_sz, inst->value, 0);
       break;
 
     case sve_size_sd:
       variant = extract_field (FLD_SVE_sz, inst->value, 0);
       break;
 

+    case sve_size_sd2:
+      variant = extract_field (FLD_SVE_sz2, inst->value, 0);
+      break;
+

     case sve_size_hsd2:
       i = extract_field (FLD_SVE_size, inst->value, 0);
       if (i < 1)
     case sve_size_hsd2:
       i = extract_field (FLD_SVE_size, inst->value, 0);
       if (i < 1)


@@ -2817,6 +2830,48 @@ aarch64_decode_variant_using_iclass (aarch64_inst *inst)
       variant = i - 1;
       break;
 
       variant = i - 1;
       break;
 

+    case sve_size_13:
+      /* Ignore low bit of this field since that is set in the opcode for
+        instructions of this iclass.  */
+      i = (extract_field (FLD_size, inst->value, 0) & 2);
+      variant = (i >> 1);
+      break;
+
+    case sve_shift_tsz_bhsd:
+      i = extract_fields (inst->value, 0, 2, FLD_SVE_tszh, FLD_SVE_tszl_19);
+      if (i == 0)
+       return FALSE;
+      while (i != 1)
+       {
+         i >>= 1;
+         variant += 1;
+       }
+      break;
+
+    case sve_size_tsz_bhs:
+      i = extract_fields (inst->value, 0, 2, FLD_SVE_sz, FLD_SVE_tszl_19);
+      if (i == 0)
+       return FALSE;
+      while (i != 1)
+       {
+         if (i & 1)
+           return FALSE;
+         i >>= 1;
+         variant += 1;
+       }
+      break;
+
+    case sve_shift_tsz_hsd:
+      i = extract_fields (inst->value, 0, 2, FLD_SVE_sz, FLD_SVE_tszl_19);
+      if (i == 0)
+       return FALSE;
+      while (i != 1)
+       {
+         i >>= 1;
+         variant += 1;
+       }
+      break;
+

     default:
       /* No mapping between instruction class and qualifiers.  */
       return TRUE;
     default:
       /* No mapping between instruction class and qualifiers.  */
       return TRUE;


@@ -2927,7 +2982,7 @@ aarch64_opcode_decode (const aarch64_opcode *opcode, const aarch64_insn code,
       DEBUG_TRACE ("constraint matching FAIL");
     }
 
       DEBUG_TRACE ("constraint matching FAIL");
     }
 

-decode_fail:
+ decode_fail:

   return FALSE;
 }
 \f
   return FALSE;
 }
 \f