- void *_this;
- int instructionLen;
- void (*err)(void*, const char*);
- const char *(*coreRegName)(void*, int);
- const char *(*auxRegName)(void*, int);
- const char *(*condCodeName)(void*, int);
- const char *(*instName)(void*, int, int, int*);
-
- unsigned char* instruction;
- unsigned index;
- const char *comm[6]; /* instr name, cond, NOP, 3 operands */
- int opWidth;
- int targets[4];
- int addresses[4];
- /* Set as a side-effect of calling the disassembler.
- Used only by the debugger. */
- enum Flow flow;
- int register_for_indirect_jump;
- int ea_reg1, ea_reg2, _offset;
- int _cond, _opcode;
- unsigned long words[2];
- char *commentBuffer;
- char instrBuffer[40];
- char operandBuffer[allOperandsSize];
- char _ea_present;
- char _mem_load;
- char _load_len;
- char nullifyMode;
- unsigned char commNum;
- unsigned char isBranch;
- unsigned char tcnt;
- unsigned char acnt;
+ /* Address of this instruction. */
+ bfd_vma address;
+
+ /* Whether this is a valid instruction. */
+ bfd_boolean valid;
+
+ insn_class_t insn_class;
+
+ /* Length (without LIMM). */
+ unsigned length;
+
+ /* Is there a LIMM in this instruction? */
+ int limm_p;
+
+ /* Long immediate value. */
+ unsigned limm_value;
+
+ /* Is it a branch/jump instruction? */
+ int is_control_flow;
+
+ /* Whether this instruction has a delay slot. */
+ int has_delay_slot;
+
+ /* Value of condition code field. */
+ enum arc_condition_code condition_code;
+
+ /* Load/store writeback mode. */
+ enum arc_ldst_writeback_mode writeback_mode;
+
+ /* Load/store data size. */
+ enum arc_ldst_data_size data_size_mode;
+
+ /* Amount of operands in instruction. Note that amount of operands
+ reported by opcodes disassembler can be different from the one
+ encoded in the instruction. Notable case is "ld a,[b,offset]",
+ when offset == 0. In this case opcodes disassembler presents
+ this instruction as "ld a,[b]", hence there are *two* operands,
+ not three. OPERANDS_COUNT and OPERANDS contain only those
+ explicit operands, hence it is up to invoker to handle the case
+ described above based on instruction opcodes. Another notable
+ thing is that in opcodes disassembler representation square
+ brackets (`[' and `]') are so called fake-operands - they are in
+ the list of operands, but do not have any value of they own.
+ Those "operands" are not present in this array. */
+ struct arc_insn_operand operands[MAX_INSN_ARGS];
+
+ unsigned int operands_count;