+ /* The fields are bits, shift, insert, extract, flags. The zero
+ index is used to indicate end-of-list. */
+#define UNUSED 0
+ { 0, 0, 0, 0, 0, 0 },
+
+#define IGNORED (UNUSED + 1)
+ { 0, 0, 0, ARC_OPERAND_IGNORE | ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK, 0, 0 },
+
+ /* The plain integer register fields. Used by 32 bit
+ instructions. */
+#define RA (IGNORED + 1)
+ { 6, 0, 0, ARC_OPERAND_IR, 0, 0 },
+#define RA_CHK (RA + 1)
+ { 6, 0, 0, ARC_OPERAND_IR, insert_ra_chk, 0 },
+#define RB (RA_CHK + 1)
+ { 6, 12, 0, ARC_OPERAND_IR, insert_rb, extract_rb },
+#define RB_CHK (RB + 1)
+ { 6, 12, 0, ARC_OPERAND_IR, insert_rb_chk, extract_rb },
+#define RC (RB_CHK + 1)
+ { 6, 6, 0, ARC_OPERAND_IR, 0, 0 },
+#define RBdup (RC + 1)
+ { 6, 12, 0, ARC_OPERAND_IR | ARC_OPERAND_DUPLICATE, insert_rb, extract_rb },
+
+#define RAD (RBdup + 1)
+ { 6, 0, 0, ARC_OPERAND_IR | ARC_OPERAND_TRUNCATE, insert_rad, 0 },
+#define RAD_CHK (RAD + 1)
+ { 6, 0, 0, ARC_OPERAND_IR | ARC_OPERAND_TRUNCATE, insert_rad, 0 },
+#define RCD (RAD_CHK + 1)
+ { 6, 6, 0, ARC_OPERAND_IR | ARC_OPERAND_TRUNCATE, insert_rcd, 0 },
+
+ /* The plain integer register fields. Used by short
+ instructions. */
+#define RA16 (RCD + 1)
+#define RA_S (RCD + 1)
+ { 4, 0, 0, ARC_OPERAND_IR, insert_ras, extract_ras },
+#define RB16 (RA16 + 1)
+#define RB_S (RA16 + 1)
+ { 4, 8, 0, ARC_OPERAND_IR, insert_rbs, extract_rbs },
+#define RB16dup (RB16 + 1)
+#define RB_Sdup (RB16 + 1)
+ { 4, 8, 0, ARC_OPERAND_IR | ARC_OPERAND_DUPLICATE, insert_rbs, extract_rbs },
+#define RC16 (RB16dup + 1)
+#define RC_S (RB16dup + 1)
+ { 4, 5, 0, ARC_OPERAND_IR, insert_rcs, extract_rcs },
+#define R6H (RC16 + 1) /* 6bit register field 'h' used
+ by V1 cpus. */
+ { 6, 5, 0, ARC_OPERAND_IR, insert_rhv1, extract_rhv1 },
+#define R5H (R6H + 1) /* 5bit register field 'h' used
+ by V2 cpus. */
+#define RH_S (R6H + 1) /* 5bit register field 'h' used
+ by V2 cpus. */
+ { 5, 5, 0, ARC_OPERAND_IR, insert_rhv2, extract_rhv2 },
+#define R5Hdup (R5H + 1)
+#define RH_Sdup (R5H + 1)
+ { 5, 5, 0, ARC_OPERAND_IR | ARC_OPERAND_DUPLICATE,
+ insert_rhv2, extract_rhv2 },
+
+#define RG (R5Hdup + 1)
+#define G_S (R5Hdup + 1)
+ { 5, 5, 0, ARC_OPERAND_IR, insert_g_s, extract_g_s },
+
+ /* Fix registers. */
+#define R0 (RG + 1)
+#define R0_S (RG + 1)
+ { 0, 0, 0, ARC_OPERAND_IR, insert_r0, extract_r0 },
+#define R1 (R0 + 1)
+#define R1_S (R0 + 1)
+ { 1, 0, 0, ARC_OPERAND_IR, insert_r1, extract_r1 },
+#define R2 (R1 + 1)
+#define R2_S (R1 + 1)
+ { 2, 0, 0, ARC_OPERAND_IR, insert_r2, extract_r2 },
+#define R3 (R2 + 1)
+#define R3_S (R2 + 1)
+ { 2, 0, 0, ARC_OPERAND_IR, insert_r3, extract_r3 },
+#define RSP (R3 + 1)
+#define SP_S (R3 + 1)
+ { 5, 0, 0, ARC_OPERAND_IR, insert_sp, extract_sp },
+#define SPdup (RSP + 1)
+#define SP_Sdup (RSP + 1)
+ { 5, 0, 0, ARC_OPERAND_IR | ARC_OPERAND_DUPLICATE, insert_sp, extract_sp },
+#define GP (SPdup + 1)
+#define GP_S (SPdup + 1)
+ { 5, 0, 0, ARC_OPERAND_IR, insert_gp, extract_gp },
+
+#define PCL_S (GP + 1)
+ { 1, 0, 0, ARC_OPERAND_IR | ARC_OPERAND_NCHK, insert_pcl, extract_pcl },
+
+#define BLINK (PCL_S + 1)
+#define BLINK_S (PCL_S + 1)
+ { 5, 0, 0, ARC_OPERAND_IR, insert_blink, extract_blink },
+
+#define ILINK1 (BLINK + 1)
+ { 5, 0, 0, ARC_OPERAND_IR, insert_ilink1, extract_ilink1 },
+#define ILINK2 (ILINK1 + 1)
+ { 5, 0, 0, ARC_OPERAND_IR, insert_ilink2, extract_ilink2 },
+
+ /* Long immediate. */
+#define LIMM (ILINK2 + 1)
+#define LIMM_S (ILINK2 + 1)
+ { 32, 0, BFD_RELOC_ARC_32_ME, ARC_OPERAND_LIMM, insert_limm, 0 },
+#define LIMMdup (LIMM + 1)
+ { 32, 0, 0, ARC_OPERAND_LIMM | ARC_OPERAND_DUPLICATE, insert_limm, 0 },
+
+ /* Special operands. */
+#define ZA (LIMMdup + 1)
+#define ZB (LIMMdup + 1)
+#define ZA_S (LIMMdup + 1)
+#define ZB_S (LIMMdup + 1)
+#define ZC_S (LIMMdup + 1)
+ { 0, 0, 0, ARC_OPERAND_UNSIGNED, insert_za, 0 },
+
+#define RRANGE_EL (ZA + 1)
+ { 4, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK | ARC_OPERAND_TRUNCATE,
+ insert_rrange, extract_rrange},
+#define R13_EL (RRANGE_EL + 1)
+ { 1, 0, 0, ARC_OPERAND_IR | ARC_OPERAND_IGNORE | ARC_OPERAND_NCHK,
+ insert_r13el, extract_rrange },
+#define FP_EL (R13_EL + 1)
+ { 1, 0, 0, ARC_OPERAND_IR | ARC_OPERAND_IGNORE | ARC_OPERAND_NCHK,
+ insert_fpel, extract_fpel },
+#define BLINK_EL (FP_EL + 1)
+ { 1, 0, 0, ARC_OPERAND_IR | ARC_OPERAND_IGNORE | ARC_OPERAND_NCHK,
+ insert_blinkel, extract_blinkel },
+#define PCL_EL (BLINK_EL + 1)
+ { 1, 0, 0, ARC_OPERAND_IR | ARC_OPERAND_IGNORE | ARC_OPERAND_NCHK,
+ insert_pclel, extract_pclel },
+
+ /* Fake operand to handle the T flag. */
+#define BRAKET (PCL_EL + 1)
+#define BRAKETdup (PCL_EL + 1)
+ { 0, 0, 0, ARC_OPERAND_FAKE | ARC_OPERAND_BRAKET, 0, 0 },
+
+ /* Fake operand to handle the T flag. */
+#define FKT_T (BRAKET + 1)
+ { 1, 3, 0, ARC_OPERAND_FAKE, insert_Ybit, 0 },
+ /* Fake operand to handle the T flag. */
+#define FKT_NT (FKT_T + 1)
+ { 1, 3, 0, ARC_OPERAND_FAKE, insert_NYbit, 0 },
+
+ /* UIMM6_20 mask = 00000000000000000000111111000000. */
+#define UIMM6_20 (FKT_NT + 1)
+ {6, 0, 0, ARC_OPERAND_UNSIGNED, insert_uimm6_20, extract_uimm6_20},
+
+ /* Exactly like the above but used by relaxation. */
+#define UIMM6_20R (UIMM6_20 + 1)
+ {6, 0, -UIMM6_20R, ARC_OPERAND_UNSIGNED | ARC_OPERAND_PCREL,
+ insert_uimm6_20, extract_uimm6_20},
+
+ /* SIMM12_20 mask = 00000000000000000000111111222222. */
+#define SIMM12_20 (UIMM6_20R + 1)
+ {12, 0, 0, ARC_OPERAND_SIGNED, insert_simm12_20, extract_simm12_20},
+
+ /* Exactly like the above but used by relaxation. */
+#define SIMM12_20R (SIMM12_20 + 1)
+ {12, 0, -SIMM12_20R, ARC_OPERAND_SIGNED | ARC_OPERAND_PCREL,
+ insert_simm12_20, extract_simm12_20},
+
+ /* UIMM12_20 mask = 00000000000000000000111111222222. */
+#define UIMM12_20 (SIMM12_20R + 1)
+ {12, 0, 0, ARC_OPERAND_UNSIGNED, insert_simm12_20, extract_uimm12_20},
+
+ /* SIMM3_5_S mask = 0000011100000000. */
+#define SIMM3_5_S (UIMM12_20 + 1)
+ {3, 0, 0, ARC_OPERAND_SIGNED | ARC_OPERAND_NCHK,
+ insert_simm3s, extract_simm3s},
+
+ /* UIMM7_A32_11_S mask = 0000000000011111. */
+#define UIMM7_A32_11_S (SIMM3_5_S + 1)
+ {7, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_ALIGNED32
+ | ARC_OPERAND_TRUNCATE | ARC_OPERAND_IGNORE, insert_uimm7_a32_11_s,
+ extract_uimm7_a32_11_s},
+
+ /* The same as above but used by relaxation. */
+#define UIMM7_A32_11R_S (UIMM7_A32_11_S + 1)
+ {7, 0, -UIMM7_A32_11R_S, ARC_OPERAND_UNSIGNED | ARC_OPERAND_ALIGNED32
+ | ARC_OPERAND_TRUNCATE | ARC_OPERAND_IGNORE | ARC_OPERAND_PCREL,
+ insert_uimm7_a32_11_s, extract_uimm7_a32_11_s},
+
+ /* UIMM7_9_S mask = 0000000001111111. */
+#define UIMM7_9_S (UIMM7_A32_11R_S + 1)
+ {7, 0, 0, ARC_OPERAND_UNSIGNED, insert_uimm7_9_s, extract_uimm7_9_s},
+
+ /* UIMM3_13_S mask = 0000000000000111. */
+#define UIMM3_13_S (UIMM7_9_S + 1)
+ {3, 0, 0, ARC_OPERAND_UNSIGNED, insert_uimm3_13_s, extract_uimm3_13_s},
+
+ /* Exactly like the above but used for relaxation. */
+#define UIMM3_13R_S (UIMM3_13_S + 1)
+ {3, 0, -UIMM3_13R_S, ARC_OPERAND_UNSIGNED | ARC_OPERAND_PCREL,
+ insert_uimm3_13_s, extract_uimm3_13_s},
+
+ /* SIMM11_A32_7_S mask = 0000000111111111. */
+#define SIMM11_A32_7_S (UIMM3_13R_S + 1)
+ {11, 0, BFD_RELOC_ARC_SDA16_LD2, ARC_OPERAND_SIGNED | ARC_OPERAND_ALIGNED32
+ | ARC_OPERAND_TRUNCATE, insert_simm11_a32_7_s, extract_simm11_a32_7_s},
+
+ /* UIMM6_13_S mask = 0000000002220111. */
+#define UIMM6_13_S (SIMM11_A32_7_S + 1)
+ {6, 0, 0, ARC_OPERAND_UNSIGNED, insert_uimm6_13_s, extract_uimm6_13_s},
+ /* UIMM5_11_S mask = 0000000000011111. */
+#define UIMM5_11_S (UIMM6_13_S + 1)
+ {5, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_IGNORE, insert_uimm5_11_s,
+ extract_uimm5_11_s},
+
+ /* SIMM9_A16_8 mask = 00000000111111102000000000000000. */
+#define SIMM9_A16_8 (UIMM5_11_S + 1)
+ {9, 0, -SIMM9_A16_8, ARC_OPERAND_SIGNED | ARC_OPERAND_ALIGNED16
+ | ARC_OPERAND_PCREL | ARC_OPERAND_TRUNCATE, insert_simm9_a16_8,
+ extract_simm9_a16_8},
+
+ /* UIMM6_8 mask = 00000000000000000000111111000000. */
+#define UIMM6_8 (SIMM9_A16_8 + 1)
+ {6, 0, 0, ARC_OPERAND_UNSIGNED, insert_uimm6_8, extract_uimm6_8},
+
+ /* SIMM21_A16_5 mask = 00000111111111102222222222000000. */
+#define SIMM21_A16_5 (UIMM6_8 + 1)
+ {21, 0, BFD_RELOC_ARC_S21H_PCREL, ARC_OPERAND_SIGNED
+ | ARC_OPERAND_ALIGNED16 | ARC_OPERAND_TRUNCATE | ARC_OPERAND_PCREL,
+ insert_simm21_a16_5, extract_simm21_a16_5},
+
+ /* SIMM25_A16_5 mask = 00000111111111102222222222003333. */
+#define SIMM25_A16_5 (SIMM21_A16_5 + 1)
+ {25, 0, BFD_RELOC_ARC_S25H_PCREL, ARC_OPERAND_SIGNED
+ | ARC_OPERAND_ALIGNED16 | ARC_OPERAND_TRUNCATE | ARC_OPERAND_PCREL,
+ insert_simm25_a16_5, extract_simm25_a16_5},
+
+ /* SIMM10_A16_7_S mask = 0000000111111111. */
+#define SIMM10_A16_7_S (SIMM25_A16_5 + 1)
+ {10, 0, -SIMM10_A16_7_S, ARC_OPERAND_SIGNED | ARC_OPERAND_ALIGNED16
+ | ARC_OPERAND_TRUNCATE | ARC_OPERAND_PCREL, insert_simm10_a16_7_s,
+ extract_simm10_a16_7_s},
+
+#define SIMM10_A16_7_Sbis (SIMM10_A16_7_S + 1)
+ {10, 0, -SIMM10_A16_7_Sbis, ARC_OPERAND_SIGNED | ARC_OPERAND_ALIGNED16
+ | ARC_OPERAND_TRUNCATE, insert_simm10_a16_7_s, extract_simm10_a16_7_s},
+
+ /* SIMM7_A16_10_S mask = 0000000000111111. */
+#define SIMM7_A16_10_S (SIMM10_A16_7_Sbis + 1)
+ {7, 0, -SIMM7_A16_10_S, ARC_OPERAND_SIGNED | ARC_OPERAND_ALIGNED16
+ | ARC_OPERAND_TRUNCATE | ARC_OPERAND_PCREL, insert_simm7_a16_10_s,
+ extract_simm7_a16_10_s},
+
+ /* SIMM21_A32_5 mask = 00000111111111002222222222000000. */
+#define SIMM21_A32_5 (SIMM7_A16_10_S + 1)
+ {21, 0, BFD_RELOC_ARC_S21W_PCREL, ARC_OPERAND_SIGNED | ARC_OPERAND_ALIGNED32
+ | ARC_OPERAND_TRUNCATE | ARC_OPERAND_PCREL, insert_simm21_a32_5,
+ extract_simm21_a32_5},
+
+ /* SIMM25_A32_5 mask = 00000111111111002222222222003333. */
+#define SIMM25_A32_5 (SIMM21_A32_5 + 1)
+ {25, 0, BFD_RELOC_ARC_S25W_PCREL, ARC_OPERAND_SIGNED | ARC_OPERAND_ALIGNED32
+ | ARC_OPERAND_TRUNCATE | ARC_OPERAND_PCREL, insert_simm25_a32_5,
+ extract_simm25_a32_5},
+
+ /* SIMM13_A32_5_S mask = 0000011111111111. */
+#define SIMM13_A32_5_S (SIMM25_A32_5 + 1)
+ {13, 0, BFD_RELOC_ARC_S13_PCREL, ARC_OPERAND_SIGNED | ARC_OPERAND_ALIGNED32
+ | ARC_OPERAND_TRUNCATE | ARC_OPERAND_PCREL, insert_simm13_a32_5_s,
+ extract_simm13_a32_5_s},
+
+ /* SIMM8_A16_9_S mask = 0000000001111111. */
+#define SIMM8_A16_9_S (SIMM13_A32_5_S + 1)
+ {8, 0, -SIMM8_A16_9_S, ARC_OPERAND_SIGNED | ARC_OPERAND_ALIGNED16
+ | ARC_OPERAND_TRUNCATE | ARC_OPERAND_PCREL, insert_simm8_a16_9_s,
+ extract_simm8_a16_9_s},
+
+/* UIMM10_6_S_JLIOFF mask = 0000001111111111. */
+#define UIMM10_6_S_JLIOFF (SIMM8_A16_9_S + 1)
+ {12, 0, BFD_RELOC_ARC_JLI_SECTOFF, ARC_OPERAND_UNSIGNED
+ | ARC_OPERAND_ALIGNED32 | ARC_OPERAND_TRUNCATE, insert_uimm10_6_s,
+ extract_uimm10_6_s},
+
+ /* UIMM3_23 mask = 00000000000000000000000111000000. */
+#define UIMM3_23 (UIMM10_6_S_JLIOFF + 1)
+ {3, 0, 0, ARC_OPERAND_UNSIGNED, insert_uimm3_23, extract_uimm3_23},
+
+ /* UIMM10_6_S mask = 0000001111111111. */
+#define UIMM10_6_S (UIMM3_23 + 1)
+ {10, 0, 0, ARC_OPERAND_UNSIGNED, insert_uimm10_6_s, extract_uimm10_6_s},
+
+ /* UIMM6_11_S mask = 0000002200011110. */
+#define UIMM6_11_S (UIMM10_6_S + 1)
+ {6, 0, 0, ARC_OPERAND_UNSIGNED, insert_uimm6_11_s, extract_uimm6_11_s},
+
+ /* SIMM9_8 mask = 00000000111111112000000000000000. */
+#define SIMM9_8 (UIMM6_11_S + 1)
+ {9, 0, BFD_RELOC_ARC_SDA_LDST, ARC_OPERAND_SIGNED | ARC_OPERAND_IGNORE,
+ insert_simm9_8, extract_simm9_8},
+
+ /* The same as above but used by relaxation. */
+#define SIMM9_8R (SIMM9_8 + 1)
+ {9, 0, -SIMM9_8R, ARC_OPERAND_SIGNED | ARC_OPERAND_IGNORE
+ | ARC_OPERAND_PCREL, insert_simm9_8, extract_simm9_8},
+
+ /* UIMM10_A32_8_S mask = 0000000011111111. */
+#define UIMM10_A32_8_S (SIMM9_8R + 1)
+ {10, 0, -UIMM10_A32_8_S, ARC_OPERAND_UNSIGNED | ARC_OPERAND_ALIGNED32
+ | ARC_OPERAND_TRUNCATE | ARC_OPERAND_PCREL, insert_uimm10_a32_8_s,
+ extract_uimm10_a32_8_s},
+
+ /* SIMM9_7_S mask = 0000000111111111. */
+#define SIMM9_7_S (UIMM10_A32_8_S + 1)
+ {9, 0, BFD_RELOC_ARC_SDA16_LD, ARC_OPERAND_SIGNED, insert_simm9_7_s,
+ extract_simm9_7_s},
+
+ /* UIMM6_A16_11_S mask = 0000000000011111. */
+#define UIMM6_A16_11_S (SIMM9_7_S + 1)
+ {6, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_ALIGNED16
+ | ARC_OPERAND_TRUNCATE | ARC_OPERAND_IGNORE, insert_uimm6_a16_11_s,
+ extract_uimm6_a16_11_s},
+
+ /* UIMM5_A32_11_S mask = 0000020000011000. */
+#define UIMM5_A32_11_S (UIMM6_A16_11_S + 1)
+ {5, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_ALIGNED32
+ | ARC_OPERAND_TRUNCATE | ARC_OPERAND_IGNORE, insert_uimm5_a32_11_s,
+ extract_uimm5_a32_11_s},
+
+ /* SIMM11_A32_13_S mask = 0000022222200111. */
+#define SIMM11_A32_13_S (UIMM5_A32_11_S + 1)
+ {11, 0, BFD_RELOC_ARC_SDA16_ST2, ARC_OPERAND_SIGNED | ARC_OPERAND_ALIGNED32
+ | ARC_OPERAND_TRUNCATE, insert_simm11_a32_13_s, extract_simm11_a32_13_s},
+
+ /* UIMM7_13_S mask = 0000000022220111. */
+#define UIMM7_13_S (SIMM11_A32_13_S + 1)
+ {7, 0, 0, ARC_OPERAND_UNSIGNED, insert_uimm7_13_s, extract_uimm7_13_s},
+
+ /* UIMM6_A16_21 mask = 00000000000000000000011111000000. */
+#define UIMM6_A16_21 (UIMM7_13_S + 1)
+ {6, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_ALIGNED16
+ | ARC_OPERAND_TRUNCATE, insert_uimm6_a16_21, extract_uimm6_a16_21},
+
+ /* UIMM7_11_S mask = 0000022200011110. */
+#define UIMM7_11_S (UIMM6_A16_21 + 1)
+ {7, 0, 0, ARC_OPERAND_UNSIGNED, insert_uimm7_11_s, extract_uimm7_11_s},
+
+ /* UIMM7_A16_20 mask = 00000000000000000000111111000000. */
+#define UIMM7_A16_20 (UIMM7_11_S + 1)
+ {7, 0, -UIMM7_A16_20, ARC_OPERAND_UNSIGNED | ARC_OPERAND_ALIGNED16
+ | ARC_OPERAND_TRUNCATE | ARC_OPERAND_PCREL, insert_uimm7_a16_20,
+ extract_uimm7_a16_20},
+
+ /* SIMM13_A16_20 mask = 00000000000000000000111111222222. */
+#define SIMM13_A16_20 (UIMM7_A16_20 + 1)
+ {13, 0, -SIMM13_A16_20, ARC_OPERAND_SIGNED | ARC_OPERAND_ALIGNED16
+ | ARC_OPERAND_TRUNCATE | ARC_OPERAND_PCREL, insert_simm13_a16_20,
+ extract_simm13_a16_20},
+
+ /* UIMM8_8_S mask = 0000000011111111. */
+#define UIMM8_8_S (SIMM13_A16_20 + 1)
+ {8, 0, 0, ARC_OPERAND_UNSIGNED, insert_uimm8_8_s, extract_uimm8_8_s},
+
+ /* The same as above but used for relaxation. */
+#define UIMM8_8R_S (UIMM8_8_S + 1)
+ {8, 0, -UIMM8_8R_S, ARC_OPERAND_UNSIGNED | ARC_OPERAND_PCREL,
+ insert_uimm8_8_s, extract_uimm8_8_s},
+
+ /* W6 mask = 00000000000000000000111111000000. */
+#define W6 (UIMM8_8R_S + 1)
+ {6, 0, 0, ARC_OPERAND_SIGNED, insert_w6, extract_w6},
+
+ /* UIMM6_5_S mask = 0000011111100000. */
+#define UIMM6_5_S (W6 + 1)
+ {6, 0, 0, ARC_OPERAND_UNSIGNED, insert_uimm6_5_s, extract_uimm6_5_s},
+
+ /* ARC NPS400 Support: See comment near head of file. */
+#define NPS_R_DST_3B (UIMM6_5_S + 1)
+ { 3, 24, 0, ARC_OPERAND_IR | ARC_OPERAND_NCHK,
+ insert_nps_3bit_reg_at_24_dst, extract_nps_3bit_reg_at_24_dst },
+
+#define NPS_R_SRC1_3B (NPS_R_DST_3B + 1)
+ { 3, 24, 0, ARC_OPERAND_IR | ARC_OPERAND_DUPLICATE | ARC_OPERAND_NCHK,
+ insert_nps_3bit_reg_at_24_dst, extract_nps_3bit_reg_at_24_dst },
+
+#define NPS_R_SRC2_3B (NPS_R_SRC1_3B + 1)
+ { 3, 21, 0, ARC_OPERAND_IR | ARC_OPERAND_NCHK,
+ insert_nps_3bit_reg_at_21_src2, extract_nps_3bit_reg_at_21_src2 },
+
+#define NPS_R_DST (NPS_R_SRC2_3B + 1)
+ { 6, 21, 0, ARC_OPERAND_IR, NULL, NULL },
+
+#define NPS_R_SRC1 (NPS_R_DST + 1)
+ { 6, 21, 0, ARC_OPERAND_IR | ARC_OPERAND_DUPLICATE, NULL, NULL },
+
+#define NPS_BITOP_DST_POS (NPS_R_SRC1 + 1)
+ { 5, 5, 0, ARC_OPERAND_UNSIGNED, 0, 0 },
+
+#define NPS_BITOP_SRC_POS (NPS_BITOP_DST_POS + 1)
+ { 5, 0, 0, ARC_OPERAND_UNSIGNED, 0, 0 },
+
+#define NPS_BITOP_SIZE (NPS_BITOP_SRC_POS + 1)
+ { 5, 10, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK,
+ insert_nps_bitop_size, extract_nps_bitop_size },
+
+#define NPS_BITOP_DST_POS_SZ (NPS_BITOP_SIZE + 1)
+ { 5, 0, 0, ARC_OPERAND_UNSIGNED,
+ insert_nps_dst_pos_and_size, extract_nps_dst_pos_and_size },
+
+#define NPS_BITOP_SIZE_2B (NPS_BITOP_DST_POS_SZ + 1)
+ { 0, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK,
+ insert_nps_bitop_size_2b, extract_nps_bitop_size_2b },
+
+#define NPS_BITOP_UIMM8 (NPS_BITOP_SIZE_2B + 1)
+ { 8, 0, 0, ARC_OPERAND_UNSIGNED,
+ insert_nps_bitop_uimm8, extract_nps_bitop_uimm8 },
+
+#define NPS_UIMM16 (NPS_BITOP_UIMM8 + 1)
+ { 16, 0, 0, ARC_OPERAND_UNSIGNED, NULL, NULL },
+
+#define NPS_SIMM16 (NPS_UIMM16 + 1)
+ { 16, 0, 0, ARC_OPERAND_SIGNED, NULL, NULL },
+
+#define NPS_RFLT_UIMM6 (NPS_SIMM16 + 1)
+ { 6, 6, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK,
+ insert_nps_rflt_uimm6, extract_nps_rflt_uimm6 },
+
+#define NPS_XLDST_UIMM16 (NPS_RFLT_UIMM6 + 1)
+ { 16, 0, BFD_RELOC_ARC_NPS_CMEM16, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK,
+ insert_nps_cmem_uimm16, extract_nps_cmem_uimm16 },
+
+#define NPS_SRC2_POS (NPS_XLDST_UIMM16 + 1)
+ { 0, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK,
+ insert_nps_src2_pos, extract_nps_src2_pos },
+
+#define NPS_SRC1_POS (NPS_SRC2_POS + 1)
+ { 0, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK,
+ insert_nps_src1_pos, extract_nps_src1_pos },
+
+#define NPS_ADDB_SIZE (NPS_SRC1_POS + 1)
+ { 0, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK,
+ insert_nps_addb_size, extract_nps_addb_size },