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Re: ARC: Use of uninitialised value
[deliverable/binutils-gdb.git]
/
opcodes
/
i386-dis.c
diff --git
a/opcodes/i386-dis.c
b/opcodes/i386-dis.c
index e6f73bff20676b7c224e716f7bcccb2feb500c80..4a59619da409f4325a72c39b2b24ca19b4a127c9 100644
(file)
--- a/
opcodes/i386-dis.c
+++ b/
opcodes/i386-dis.c
@@
-401,11
+401,9
@@
fetch_data (struct disassemble_info *info, bfd_byte *addr)
#define EXxmm_mw { OP_EX, xmm_mw_mode }
#define EXxmm_md { OP_EX, xmm_md_mode }
#define EXxmm_mq { OP_EX, xmm_mq_mode }
#define EXxmm_mw { OP_EX, xmm_mw_mode }
#define EXxmm_md { OP_EX, xmm_md_mode }
#define EXxmm_mq { OP_EX, xmm_mq_mode }
-#define EXxmm_mdq { OP_EX, xmm_mdq_mode }
#define EXxmmdw { OP_EX, xmmdw_mode }
#define EXxmmqd { OP_EX, xmmqd_mode }
#define EXymmq { OP_EX, ymmq_mode }
#define EXxmmdw { OP_EX, xmmdw_mode }
#define EXxmmqd { OP_EX, xmmqd_mode }
#define EXymmq { OP_EX, ymmq_mode }
-#define EXVexWdq { OP_EX, vex_w_dq_mode }
#define EXVexWdqScalar { OP_EX, vex_scalar_w_dq_mode }
#define EXEvexXGscat { OP_EX, evex_x_gscat_mode }
#define EXEvexXNoBcst { OP_EX, evex_x_nobcst_mode }
#define EXVexWdqScalar { OP_EX, vex_scalar_w_dq_mode }
#define EXEvexXGscat { OP_EX, evex_x_gscat_mode }
#define EXEvexXNoBcst { OP_EX, evex_x_nobcst_mode }
@@
-538,9
+536,6
@@
enum
xmm_md_mode,
/* XMM register or quad word memory operand */
xmm_mq_mode,
xmm_md_mode,
/* XMM register or quad word memory operand */
xmm_mq_mode,
- /* XMM register or double/quad word memory operand, depending on
- VEX.W. */
- xmm_mdq_mode,
/* 16-byte XMM, word, double word or quad word operand. */
xmmdw_mode,
/* 16-byte XMM, double word, quad word operand or xmm word operand. */
/* 16-byte XMM, word, double word or quad word operand. */
xmmdw_mode,
/* 16-byte XMM, double word, quad word operand or xmm word operand. */
@@
-595,14
+590,12
@@
enum
vex128_mode,
/* 256bit vex mode */
vex256_mode,
vex128_mode,
/* 256bit vex mode */
vex256_mode,
- /* operand size depends on the VEX.W bit. */
- vex_w_dq_mode,
- /*
Similar to vex_w_dq_mode
, with VSIB dword indices. */
+ /*
Operand size depends on the VEX.W bit
, with VSIB dword indices. */
vex_vsib_d_w_dq_mode,
/* Similar to vex_vsib_d_w_dq_mode, with smaller memory. */
vex_vsib_d_w_d_mode,
vex_vsib_d_w_dq_mode,
/* Similar to vex_vsib_d_w_dq_mode, with smaller memory. */
vex_vsib_d_w_d_mode,
- /*
Similar to vex_w_dq_mode
, with VSIB qword indices. */
+ /*
Operand size depends on the VEX.W bit
, with VSIB qword indices. */
vex_vsib_q_w_dq_mode,
/* Similar to vex_vsib_q_w_dq_mode, with smaller memory. */
vex_vsib_q_w_d_mode,
vex_vsib_q_w_dq_mode,
/* Similar to vex_vsib_q_w_dq_mode, with smaller memory. */
vex_vsib_q_w_d_mode,
@@
-623,7
+616,7
@@
enum
q_scalar_swap_mode,
/* like vex_mode, ignore vector length. */
vex_scalar_mode,
q_scalar_swap_mode,
/* like vex_mode, ignore vector length. */
vex_scalar_mode,
- /*
like vex_w_dq_mode
, ignore vector length. */
+ /*
Operand size depends on the VEX.W bit
, ignore vector length. */
vex_scalar_w_dq_mode,
/* Static rounding. */
vex_scalar_w_dq_mode,
/* Static rounding. */
@@
-966,6
+959,7
@@
enum
enum
{
PREFIX_90 = 0,
enum
{
PREFIX_90 = 0,
+ PREFIX_0F01_REG_3_RM_1,
PREFIX_0F01_REG_5_MOD_0,
PREFIX_0F01_REG_5_MOD_3_RM_0,
PREFIX_0F01_REG_5_MOD_3_RM_2,
PREFIX_0F01_REG_5_MOD_0,
PREFIX_0F01_REG_5_MOD_3_RM_0,
PREFIX_0F01_REG_5_MOD_3_RM_2,
@@
-1747,7
+1741,7
@@
enum
{
X86_64_06 = 0,
X86_64_07,
{
X86_64_06 = 0,
X86_64_07,
- X86_64_0
D
,
+ X86_64_0
E
,
X86_64_16,
X86_64_17,
X86_64_1E,
X86_64_16,
X86_64_17,
X86_64_1E,
@@
-1764,6
+1758,8
@@
enum
X86_64_6F,
X86_64_82,
X86_64_9A,
X86_64_6F,
X86_64_82,
X86_64_9A,
+ X86_64_C2,
+ X86_64_C3,
X86_64_C4,
X86_64_C5,
X86_64_CE,
X86_64_C4,
X86_64_C5,
X86_64_CE,
@@
-2336,8
+2332,8
@@
struct dis386 {
'Z' => print 'q' in 64bit mode and behave as 'L' otherwise
'!' => change condition from true to false or from false to true.
'%' => add 1 upper case letter to the macro.
'Z' => print 'q' in 64bit mode and behave as 'L' otherwise
'!' => change condition from true to false or from false to true.
'%' => add 1 upper case letter to the macro.
- '^' => print 'w'
or 'l' depending on operand size prefix or
- suffix_always is true (lcall/ljmp).
+ '^' => print 'w'
, 'l', or 'q' (Intel64 ISA only) depending on operand size
+
prefix or
suffix_always is true (lcall/ljmp).
'@' => print 'q' for Intel64 ISA, 'w' or 'q' for AMD64 ISA depending
on operand size prefix.
'&' => print 'q' in 64bit mode for Intel64 ISA or if instruction
'@' => print 'q' for Intel64 ISA, 'w' or 'q' for AMD64 ISA depending
on operand size prefix.
'&' => print 'q' in 64bit mode for Intel64 ISA or if instruction
@@
-2383,7
+2379,7
@@
static const struct dis386 dis386[] = {
{ "orS", { Gv, EvS }, 0 },
{ "orB", { AL, Ib }, 0 },
{ "orS", { eAX, Iv }, 0 },
{ "orS", { Gv, EvS }, 0 },
{ "orB", { AL, Ib }, 0 },
{ "orS", { eAX, Iv }, 0 },
- { X86_64_TABLE (X86_64_0
D
) },
+ { X86_64_TABLE (X86_64_0
E
) },
{ Bad_Opcode }, /* 0x0f extended opcode escape */
/* 10 */
{ "adcB", { Ebh1, Gb }, 0 },
{ Bad_Opcode }, /* 0x0f extended opcode escape */
/* 10 */
{ "adcB", { Ebh1, Gb }, 0 },
@@
-2586,8
+2582,8
@@
static const struct dis386 dis386[] = {
/* c0 */
{ REG_TABLE (REG_C0) },
{ REG_TABLE (REG_C1) },
/* c0 */
{ REG_TABLE (REG_C0) },
{ REG_TABLE (REG_C1) },
- {
"retT", { Iw, BND }, 0
},
- {
"retT", { BND }, 0
},
+ {
X86_64_TABLE (X86_64_C2)
},
+ {
X86_64_TABLE (X86_64_C3)
},
{ X86_64_TABLE (X86_64_C4) },
{ X86_64_TABLE (X86_64_C5) },
{ REG_TABLE (REG_C6) },
{ X86_64_TABLE (X86_64_C4) },
{ X86_64_TABLE (X86_64_C5) },
{ REG_TABLE (REG_C6) },
@@
-3632,6
+3628,14
@@
static const struct dis386 prefix_table[][4] = {
{ NULL, { { NULL, 0 } }, PREFIX_IGNORED }
},
{ NULL, { { NULL, 0 } }, PREFIX_IGNORED }
},
+ /* PREFIX_0F01_REG_3_MOD_1 */
+ {
+ { "vmmcall", { Skip_MODRM }, 0 },
+ { "vmgexit", { Skip_MODRM }, 0 },
+ { Bad_Opcode },
+ { "vmgexit", { Skip_MODRM }, 0 },
+ },
+
/* PREFIX_0F01_REG_5_MOD_0 */
{
{ Bad_Opcode },
/* PREFIX_0F01_REG_5_MOD_0 */
{
{ Bad_Opcode },
@@
-6811,7
+6815,7
@@
static const struct dis386 x86_64_table[][2] = {
{ "popP", { es }, 0 },
},
{ "popP", { es }, 0 },
},
- /* X86_64_0
D
*/
+ /* X86_64_0
E
*/
{
{ "pushP", { cs }, 0 },
},
{
{ "pushP", { cs }, 0 },
},
@@
-6901,6
+6905,18
@@
static const struct dis386 x86_64_table[][2] = {
{ "Jcall{T|}", { Ap }, 0 },
},
{ "Jcall{T|}", { Ap }, 0 },
},
+ /* X86_64_C2 */
+ {
+ { "retP", { Iw, BND }, 0 },
+ { "ret@", { Iw, BND }, 0 },
+ },
+
+ /* X86_64_C3 */
+ {
+ { "retP", { BND }, 0 },
+ { "ret@", { BND }, 0 },
+ },
+
/* X86_64_C4 */
{
{ MOD_TABLE (MOD_C4_32BIT) },
/* X86_64_C4 */
{
{ MOD_TABLE (MOD_C4_32BIT) },
@@
-11011,7
+11027,7
@@
static const struct dis386 rm_table[][8] = {
{
/* RM_0F01_REG_3 */
{ "vmrun", { Skip_MODRM }, 0 },
{
/* RM_0F01_REG_3 */
{ "vmrun", { Skip_MODRM }, 0 },
- {
"vmmcall", { Skip_MODRM }, 0
},
+ {
PREFIX_TABLE (PREFIX_0F01_REG_3_RM_1)
},
{ "vmload", { Skip_MODRM }, 0 },
{ "vmsave", { Skip_MODRM }, 0 },
{ "stgi", { Skip_MODRM }, 0 },
{ "vmload", { Skip_MODRM }, 0 },
{ "vmsave", { Skip_MODRM }, 0 },
{ "stgi", { Skip_MODRM }, 0 },
@@
-12784,7
+12800,7
@@
putop (const char *in_template, int sizeflag)
case 'B':
if (l == 0 && len == 1)
{
case 'B':
if (l == 0 && len == 1)
{
-case_B:
+
case_B:
if (intel_syntax)
break;
if (sizeflag & SUFFIX_ALWAYS)
if (intel_syntax)
break;
if (sizeflag & SUFFIX_ALWAYS)
@@
-12949,7
+12965,7
@@
case_B:
SAVE_LAST (*p);
break;
}
SAVE_LAST (*p);
break;
}
-case_L:
+
case_L:
if (intel_syntax)
break;
if (sizeflag & SUFFIX_ALWAYS)
if (intel_syntax)
break;
if (sizeflag & SUFFIX_ALWAYS)
@@
-12998,7
+13014,7
@@
case_L:
case 'P':
if (l == 0 && len == 1)
{
case 'P':
if (l == 0 && len == 1)
{
-case_P:
+
case_P:
if (intel_syntax)
{
if ((rex & REX_W) == 0
if (intel_syntax)
{
if ((rex & REX_W) == 0
@@
-13068,7
+13084,7
@@
case_P:
case 'Q':
if (l == 0 && len == 1)
{
case 'Q':
if (l == 0 && len == 1)
{
-case_Q:
+
case_Q:
if (intel_syntax && !alt)
break;
USED_REX (REX_W);
if (intel_syntax && !alt)
break;
USED_REX (REX_W);
@@
-13159,7
+13175,7
@@
case_Q:
case 'S':
if (l == 0 && len == 1)
{
case 'S':
if (l == 0 && len == 1)
{
-case_S:
+
case_S:
if (intel_syntax)
break;
if (sizeflag & SUFFIX_ALWAYS)
if (intel_syntax)
break;
if (sizeflag & SUFFIX_ALWAYS)
@@
-13289,6
+13305,12
@@
case_S:
case '^':
if (intel_syntax)
break;
case '^':
if (intel_syntax)
break;
+ if (isa64 == intel64 && (rex & REX_W))
+ {
+ USED_REX (REX_W);
+ *obufp++ = 'q';
+ break;
+ }
if ((prefixes & PREFIX_DATA) || (sizeflag & SUFFIX_ALWAYS))
{
if (sizeflag & DFLAG)
if ((prefixes & PREFIX_DATA) || (sizeflag & SUFFIX_ALWAYS))
{
if (sizeflag & DFLAG)
@@
-13760,8
+13782,6
@@
intel_operand_size (int bytemode, int sizeflag)
case o_mode:
oappend ("OWORD PTR ");
break;
case o_mode:
oappend ("OWORD PTR ");
break;
- case xmm_mdq_mode:
- case vex_w_dq_mode:
case vex_scalar_w_dq_mode:
if (!need_vex)
abort ();
case vex_scalar_w_dq_mode:
if (!need_vex)
abort ();
@@
-14006,12
+14026,12
@@
OP_E_memory (int bytemode, int sizeflag)
break;
}
/* fall through */
break;
}
/* fall through */
+ case vex_scalar_w_dq_mode:
case vex_vsib_d_w_dq_mode:
case vex_vsib_d_w_d_mode:
case vex_vsib_q_w_dq_mode:
case vex_vsib_q_w_d_mode:
case evex_x_gscat_mode:
case vex_vsib_d_w_dq_mode:
case vex_vsib_d_w_d_mode:
case vex_vsib_q_w_dq_mode:
case vex_vsib_q_w_d_mode:
case evex_x_gscat_mode:
- case xmm_mdq_mode:
shift = vex.w ? 3 : 2;
break;
case x_mode:
shift = vex.w ? 3 : 2;
break;
case x_mode:
@@
-14252,10
+14272,11
@@
OP_E_memory (int bytemode, int sizeflag)
}
if ((havebase || haveindex || needindex || needaddr32 || riprel)
}
if ((havebase || haveindex || needindex || needaddr32 || riprel)
- && (bytemode != v_bnd_mode)
- && (bytemode != v_bndmk_mode)
- && (bytemode != bnd_mode)
- && (bytemode != bnd_swap_mode))
+ && (address_mode != mode_64bit
+ || ((bytemode != v_bnd_mode)
+ && (bytemode != v_bndmk_mode)
+ && (bytemode != bnd_mode)
+ && (bytemode != bnd_swap_mode))))
used_prefixes |= PREFIX_ADDR;
if (havedisp || (intel_syntax && riprel))
used_prefixes |= PREFIX_ADDR;
if (havedisp || (intel_syntax && riprel))
@@
-14336,6
+14357,14
@@
OP_E_memory (int bytemode, int sizeflag)
}
}
}
}
}
}
+ else if (bytemode == v_bnd_mode
+ || bytemode == v_bndmk_mode
+ || bytemode == bnd_mode
+ || bytemode == bnd_swap_mode)
+ {
+ oappend ("(bad)");
+ return;
+ }
else
{
/* 16 bit address mode */
else
{
/* 16 bit address mode */
@@
-15357,7
+15386,6
@@
OP_EX (int bytemode, int sizeflag)
&& bytemode != xmm_mw_mode
&& bytemode != xmm_md_mode
&& bytemode != xmm_mq_mode
&& bytemode != xmm_mw_mode
&& bytemode != xmm_md_mode
&& bytemode != xmm_mq_mode
- && bytemode != xmm_mdq_mode
&& bytemode != xmmq_mode
&& bytemode != evex_half_bcst_xmmq_mode
&& bytemode != ymm_mode
&& bytemode != xmmq_mode
&& bytemode != evex_half_bcst_xmmq_mode
&& bytemode != ymm_mode
@@
-15854,7
+15882,7
@@
CRC32_Fixup (int bytemode, int sizeflag)
mnemonicendp = p;
*p = '\0';
mnemonicendp = p;
*p = '\0';
-skip:
+
skip:
if (modrm.mod == 3)
{
int add;
if (modrm.mod == 3)
{
int add;
@@
-16577,7
+16605,7
@@
MOVBE_Fixup (int bytemode, int sizeflag)
mnemonicendp = p;
*p = '\0';
mnemonicendp = p;
*p = '\0';
-skip:
+
skip:
OP_M (bytemode, sizeflag);
}
OP_M (bytemode, sizeflag);
}
@@
-16614,7
+16642,7
@@
MOVSXD_Fixup (int bytemode, int sizeflag)
break;
}
break;
}
-skip:
+
skip:
mnemonicendp = p;
*p = '\0';
OP_E (bytemode, sizeflag);
mnemonicendp = p;
*p = '\0';
OP_E (bytemode, sizeflag);
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