projects
/
deliverable
/
binutils-gdb.git
/ blobdiff
commit
grep
author
committer
pickaxe
?
search:
re
summary
|
shortlog
|
log
|
commit
|
commitdiff
|
tree
raw
|
inline
| side by side
gas/
[deliverable/binutils-gdb.git]
/
opcodes
/
i386-opc.h
diff --git
a/opcodes/i386-opc.h
b/opcodes/i386-opc.h
index f76b9863cd631840538569e9cb4f1be020621f1f..0dda2a47bdf9368c9123e38ed46f1997e6c0353d 100644
(file)
--- a/
opcodes/i386-opc.h
+++ b/
opcodes/i386-opc.h
@@
-78,8
+78,10
@@
#define CpuSSE4_1 (CpuABM + 1)
/* SSE4.2 support required */
#define CpuSSE4_2 (CpuSSE4_1 + 1)
#define CpuSSE4_1 (CpuABM + 1)
/* SSE4.2 support required */
#define CpuSSE4_2 (CpuSSE4_1 + 1)
+/* SSE5 support required */
+#define CpuSSE5 (CpuSSE4_2 + 1)
/* 64bit support available, used by -march= in assembler. */
/* 64bit support available, used by -march= in assembler. */
-#define CpuLM (CpuSSE
4_2
+ 1)
+#define CpuLM (CpuSSE
5
+ 1)
/* 64bit support required */
#define Cpu64 (CpuLM + 1)
/* Not supported in the 64bit mode */
/* 64bit support required */
#define Cpu64 (CpuLM + 1)
/* Not supported in the 64bit mode */
@@
-126,6
+128,7
@@
typedef union i386_cpu_flags
unsigned int cpuabm:1;
unsigned int cpusse4_1:1;
unsigned int cpusse4_2:1;
unsigned int cpuabm:1;
unsigned int cpusse4_1:1;
unsigned int cpusse4_2:1;
+ unsigned int cpusse5:1;
unsigned int cpulm:1;
unsigned int cpu64:1;
unsigned int cpuno64:1;
unsigned int cpulm:1;
unsigned int cpu64:1;
unsigned int cpuno64:1;
@@
-199,8
+202,13
@@
typedef union i386_cpu_flags
#define Rex64 (NoRex64 + 1)
/* deprecated fp insn, gets a warning */
#define Ugh (Rex64 + 1)
#define Rex64 (NoRex64 + 1)
/* deprecated fp insn, gets a warning */
#define Ugh (Rex64 + 1)
+#define Drex (Ugh + 1)
+/* instruction needs DREX with multiple encodings for memory ops */
+#define Drexv (Drex + 1)
+/* special DREX for comparisons */
+#define Drexc (Drexv + 1)
/* The last bitfield in i386_opcode_modifier. */
/* The last bitfield in i386_opcode_modifier. */
-#define Opcode_Modifier_Max
Ugh
+#define Opcode_Modifier_Max
Drexc
typedef struct i386_opcode_modifier
{
typedef struct i386_opcode_modifier
{
@@
-234,6
+242,9
@@
typedef struct i386_opcode_modifier
unsigned int norex64:1;
unsigned int rex64:1;
unsigned int ugh:1;
unsigned int norex64:1;
unsigned int rex64:1;
unsigned int ugh:1;
+ unsigned int drex:1;
+ unsigned int drexv:1;
+ unsigned int drexc:1;
} i386_opcode_modifier;
/* Position of operand_type bits. */
} i386_opcode_modifier;
/* Position of operand_type bits. */
@@
-400,7
+411,8
@@
typedef struct template
/* extension_opcode is the 3 bit extension for group <n> insns.
This field is also used to store the 8-bit opcode suffix for the
AMD 3DNow! instructions.
/* extension_opcode is the 3 bit extension for group <n> insns.
This field is also used to store the 8-bit opcode suffix for the
AMD 3DNow! instructions.
- If this template has no extension opcode (the usual case) use None */
+ If this template has no extension opcode (the usual case) use None
+ Instructions with Drex use this to specify 2 bits for OC */
unsigned int extension_opcode;
#define None 0xffff /* If no extension_opcode is possible. */
unsigned int extension_opcode;
#define None 0xffff /* If no extension_opcode is possible. */
@@
-431,6
+443,10
@@
typedef struct
#define RegRex 0x1 /* Extended register. */
#define RegRex64 0x2 /* Extended 8 bit register. */
unsigned int reg_num;
#define RegRex 0x1 /* Extended register. */
#define RegRex64 0x2 /* Extended 8 bit register. */
unsigned int reg_num;
+#define RegRip ((unsigned int ) ~0)
+/* EIZ and RIZ are fake index registers. */
+#define RegEiz (RegRip - 1)
+#define RegRiz (RegEiz - 1)
}
reg_entry;
}
reg_entry;
This page took
0.030415 seconds
and
4
git commands to generate.