-mm0, RegMMX, 0, 0, 29, 41
-mm1, RegMMX, 0, 1, 30, 42
-mm2, RegMMX, 0, 2, 31, 43
-mm3, RegMMX, 0, 3, 32, 44
-mm4, RegMMX, 0, 4, 33, 45
-mm5, RegMMX, 0, 5, 34, 46
-mm6, RegMMX, 0, 6, 35, 47
-mm7, RegMMX, 0, 7, 36, 48
-xmm0, RegXMM|Acc, 0, 0, 21, 17
-xmm1, RegXMM, 0, 1, 22, 18
-xmm2, RegXMM, 0, 2, 23, 19
-xmm3, RegXMM, 0, 3, 24, 20
-xmm4, RegXMM, 0, 4, 25, 21
-xmm5, RegXMM, 0, 5, 26, 22
-xmm6, RegXMM, 0, 6, 27, 23
-xmm7, RegXMM, 0, 7, 28, 24
-xmm8, RegXMM, RegRex, 0, Dw2Inval, 25
-xmm9, RegXMM, RegRex, 1, Dw2Inval, 26
-xmm10, RegXMM, RegRex, 2, Dw2Inval, 27
-xmm11, RegXMM, RegRex, 3, Dw2Inval, 28
-xmm12, RegXMM, RegRex, 4, Dw2Inval, 29
-xmm13, RegXMM, RegRex, 5, Dw2Inval, 30
-xmm14, RegXMM, RegRex, 6, Dw2Inval, 31
-xmm15, RegXMM, RegRex, 7, Dw2Inval, 32
-xmm16, RegXMM, RegVRex, 0, Dw2Inval, 67
-xmm17, RegXMM, RegVRex, 1, Dw2Inval, 68
-xmm18, RegXMM, RegVRex, 2, Dw2Inval, 69
-xmm19, RegXMM, RegVRex, 3, Dw2Inval, 70
-xmm20, RegXMM, RegVRex, 4, Dw2Inval, 71
-xmm21, RegXMM, RegVRex, 5, Dw2Inval, 72
-xmm22, RegXMM, RegVRex, 6, Dw2Inval, 73
-xmm23, RegXMM, RegVRex, 7, Dw2Inval, 74
-xmm24, RegXMM, RegVRex|RegRex, 0, Dw2Inval, 75
-xmm25, RegXMM, RegVRex|RegRex, 1, Dw2Inval, 76
-xmm26, RegXMM, RegVRex|RegRex, 2, Dw2Inval, 77
-xmm27, RegXMM, RegVRex|RegRex, 3, Dw2Inval, 78
-xmm28, RegXMM, RegVRex|RegRex, 4, Dw2Inval, 79
-xmm29, RegXMM, RegVRex|RegRex, 5, Dw2Inval, 80
-xmm30, RegXMM, RegVRex|RegRex, 6, Dw2Inval, 81
-xmm31, RegXMM, RegVRex|RegRex, 7, Dw2Inval, 82
+mm0, Class=RegMMX, 0, 0, 29, 41
+mm1, Class=RegMMX, 0, 1, 30, 42
+mm2, Class=RegMMX, 0, 2, 31, 43
+mm3, Class=RegMMX, 0, 3, 32, 44
+mm4, Class=RegMMX, 0, 4, 33, 45
+mm5, Class=RegMMX, 0, 5, 34, 46
+mm6, Class=RegMMX, 0, 6, 35, 47
+mm7, Class=RegMMX, 0, 7, 36, 48
+xmm0, Class=RegSIMD|Instance=Accum|Xmmword, 0, 0, 21, 17
+xmm1, Class=RegSIMD|Xmmword, 0, 1, 22, 18
+xmm2, Class=RegSIMD|Xmmword, 0, 2, 23, 19
+xmm3, Class=RegSIMD|Xmmword, 0, 3, 24, 20
+xmm4, Class=RegSIMD|Xmmword, 0, 4, 25, 21
+xmm5, Class=RegSIMD|Xmmword, 0, 5, 26, 22
+xmm6, Class=RegSIMD|Xmmword, 0, 6, 27, 23
+xmm7, Class=RegSIMD|Xmmword, 0, 7, 28, 24
+xmm8, Class=RegSIMD|Xmmword, RegRex, 0, Dw2Inval, 25
+xmm9, Class=RegSIMD|Xmmword, RegRex, 1, Dw2Inval, 26
+xmm10, Class=RegSIMD|Xmmword, RegRex, 2, Dw2Inval, 27
+xmm11, Class=RegSIMD|Xmmword, RegRex, 3, Dw2Inval, 28
+xmm12, Class=RegSIMD|Xmmword, RegRex, 4, Dw2Inval, 29
+xmm13, Class=RegSIMD|Xmmword, RegRex, 5, Dw2Inval, 30
+xmm14, Class=RegSIMD|Xmmword, RegRex, 6, Dw2Inval, 31
+xmm15, Class=RegSIMD|Xmmword, RegRex, 7, Dw2Inval, 32
+xmm16, Class=RegSIMD|Xmmword, RegVRex, 0, Dw2Inval, 67
+xmm17, Class=RegSIMD|Xmmword, RegVRex, 1, Dw2Inval, 68
+xmm18, Class=RegSIMD|Xmmword, RegVRex, 2, Dw2Inval, 69
+xmm19, Class=RegSIMD|Xmmword, RegVRex, 3, Dw2Inval, 70
+xmm20, Class=RegSIMD|Xmmword, RegVRex, 4, Dw2Inval, 71
+xmm21, Class=RegSIMD|Xmmword, RegVRex, 5, Dw2Inval, 72
+xmm22, Class=RegSIMD|Xmmword, RegVRex, 6, Dw2Inval, 73
+xmm23, Class=RegSIMD|Xmmword, RegVRex, 7, Dw2Inval, 74
+xmm24, Class=RegSIMD|Xmmword, RegVRex|RegRex, 0, Dw2Inval, 75
+xmm25, Class=RegSIMD|Xmmword, RegVRex|RegRex, 1, Dw2Inval, 76
+xmm26, Class=RegSIMD|Xmmword, RegVRex|RegRex, 2, Dw2Inval, 77
+xmm27, Class=RegSIMD|Xmmword, RegVRex|RegRex, 3, Dw2Inval, 78
+xmm28, Class=RegSIMD|Xmmword, RegVRex|RegRex, 4, Dw2Inval, 79
+xmm29, Class=RegSIMD|Xmmword, RegVRex|RegRex, 5, Dw2Inval, 80
+xmm30, Class=RegSIMD|Xmmword, RegVRex|RegRex, 6, Dw2Inval, 81
+xmm31, Class=RegSIMD|Xmmword, RegVRex|RegRex, 7, Dw2Inval, 82