- { M32R_F_NIL, "f-nil", 0, 0, 0, 0, { 0, { (1<<MACH_BASE) } } },
- { M32R_F_OP1, "f-op1", 0, 32, 0, 4, { 0, { (1<<MACH_BASE) } } },
- { M32R_F_OP2, "f-op2", 0, 32, 8, 4, { 0, { (1<<MACH_BASE) } } },
- { M32R_F_COND, "f-cond", 0, 32, 4, 4, { 0, { (1<<MACH_BASE) } } },
- { M32R_F_R1, "f-r1", 0, 32, 4, 4, { 0, { (1<<MACH_BASE) } } },
- { M32R_F_R2, "f-r2", 0, 32, 12, 4, { 0, { (1<<MACH_BASE) } } },
- { M32R_F_SIMM8, "f-simm8", 0, 32, 8, 8, { 0, { (1<<MACH_BASE) } } },
- { M32R_F_SIMM16, "f-simm16", 0, 32, 16, 16, { 0, { (1<<MACH_BASE) } } },
- { M32R_F_SHIFT_OP2, "f-shift-op2", 0, 32, 8, 3, { 0, { (1<<MACH_BASE) } } },
- { M32R_F_UIMM4, "f-uimm4", 0, 32, 12, 4, { 0, { (1<<MACH_BASE) } } },
- { M32R_F_UIMM5, "f-uimm5", 0, 32, 11, 5, { 0, { (1<<MACH_BASE) } } },
- { M32R_F_UIMM16, "f-uimm16", 0, 32, 16, 16, { 0, { (1<<MACH_BASE) } } },
- { M32R_F_UIMM24, "f-uimm24", 0, 32, 8, 24, { 0|A(RELOC)|A(ABS_ADDR), { (1<<MACH_BASE) } } },
- { M32R_F_HI16, "f-hi16", 0, 32, 16, 16, { 0|A(SIGN_OPT), { (1<<MACH_BASE) } } },
- { M32R_F_DISP8, "f-disp8", 0, 32, 8, 8, { 0|A(RELOC)|A(PCREL_ADDR), { (1<<MACH_BASE) } } },
- { M32R_F_DISP16, "f-disp16", 0, 32, 16, 16, { 0|A(RELOC)|A(PCREL_ADDR), { (1<<MACH_BASE) } } },
- { M32R_F_DISP24, "f-disp24", 0, 32, 8, 24, { 0|A(RELOC)|A(PCREL_ADDR), { (1<<MACH_BASE) } } },
- { M32R_F_OP23, "f-op23", 0, 32, 9, 3, { 0, { (1<<MACH_BASE) } } },
- { M32R_F_OP3, "f-op3", 0, 32, 14, 2, { 0, { (1<<MACH_BASE) } } },
- { M32R_F_ACC, "f-acc", 0, 32, 8, 1, { 0, { (1<<MACH_BASE) } } },
- { M32R_F_ACCS, "f-accs", 0, 32, 12, 2, { 0, { (1<<MACH_BASE) } } },
- { M32R_F_ACCD, "f-accd", 0, 32, 4, 2, { 0, { (1<<MACH_BASE) } } },
- { M32R_F_BITS67, "f-bits67", 0, 32, 6, 2, { 0, { (1<<MACH_BASE) } } },
- { M32R_F_BIT14, "f-bit14", 0, 32, 14, 1, { 0, { (1<<MACH_BASE) } } },
- { M32R_F_IMM1, "f-imm1", 0, 32, 15, 1, { 0, { (1<<MACH_BASE) } } },
- { 0 }
+ { M32R_F_NIL, "f-nil", 0, 0, 0, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ { M32R_F_ANYOF, "f-anyof", 0, 0, 0, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ { M32R_F_OP1, "f-op1", 0, 32, 0, 4, { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ { M32R_F_OP2, "f-op2", 0, 32, 8, 4, { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ { M32R_F_COND, "f-cond", 0, 32, 4, 4, { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ { M32R_F_R1, "f-r1", 0, 32, 4, 4, { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ { M32R_F_R2, "f-r2", 0, 32, 12, 4, { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ { M32R_F_SIMM8, "f-simm8", 0, 32, 8, 8, { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ { M32R_F_SIMM16, "f-simm16", 0, 32, 16, 16, { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ { M32R_F_SHIFT_OP2, "f-shift-op2", 0, 32, 8, 3, { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ { M32R_F_UIMM3, "f-uimm3", 0, 32, 5, 3, { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ { M32R_F_UIMM4, "f-uimm4", 0, 32, 12, 4, { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ { M32R_F_UIMM5, "f-uimm5", 0, 32, 11, 5, { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ { M32R_F_UIMM8, "f-uimm8", 0, 32, 8, 8, { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ { M32R_F_UIMM16, "f-uimm16", 0, 32, 16, 16, { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ { M32R_F_UIMM24, "f-uimm24", 0, 32, 8, 24, { 0|A(RELOC)|A(ABS_ADDR), { { { (1<<MACH_BASE), 0 } } } } },
+ { M32R_F_HI16, "f-hi16", 0, 32, 16, 16, { 0|A(SIGN_OPT), { { { (1<<MACH_BASE), 0 } } } } },
+ { M32R_F_DISP8, "f-disp8", 0, 32, 8, 8, { 0|A(RELOC)|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } } } } },
+ { M32R_F_DISP16, "f-disp16", 0, 32, 16, 16, { 0|A(RELOC)|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } } } } },
+ { M32R_F_DISP24, "f-disp24", 0, 32, 8, 24, { 0|A(RELOC)|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } } } } },
+ { M32R_F_OP23, "f-op23", 0, 32, 9, 3, { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ { M32R_F_OP3, "f-op3", 0, 32, 14, 2, { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ { M32R_F_ACC, "f-acc", 0, 32, 8, 1, { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ { M32R_F_ACCS, "f-accs", 0, 32, 12, 2, { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ { M32R_F_ACCD, "f-accd", 0, 32, 4, 2, { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ { M32R_F_BITS67, "f-bits67", 0, 32, 6, 2, { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ { M32R_F_BIT4, "f-bit4", 0, 32, 4, 1, { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ { M32R_F_BIT14, "f-bit14", 0, 32, 14, 1, { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ { M32R_F_IMM1, "f-imm1", 0, 32, 15, 1, { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ { 0, 0, 0, 0, 0, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } }