-static CGEN_HW_ENTRY m32r_cgen_hw_entries[] =
-{
- { "h-pc", CGEN_ASM_KEYWORD, (PTR) 0 },
- { "h-memory", CGEN_ASM_KEYWORD, (PTR) 0 },
- { "h-sint", CGEN_ASM_KEYWORD, (PTR) 0 },
- { "h-uint", CGEN_ASM_KEYWORD, (PTR) 0 },
- { "h-addr", CGEN_ASM_KEYWORD, (PTR) 0 },
- { "h-iaddr", CGEN_ASM_KEYWORD, (PTR) 0 },
- { "h-hi16", CGEN_ASM_KEYWORD, (PTR) 0 },
- { "h-slo16", CGEN_ASM_KEYWORD, (PTR) 0 },
- { "h-ulo16", CGEN_ASM_KEYWORD, (PTR) 0 },
- { "h-gr", CGEN_ASM_KEYWORD, (PTR) & m32r_cgen_opval_h_gr },
- { "h-cr", CGEN_ASM_KEYWORD, (PTR) & m32r_cgen_opval_h_cr },
- { "h-accum", CGEN_ASM_KEYWORD, (PTR) 0 },
-/* start-sanitize-m32rx */
- { "h-accums", CGEN_ASM_KEYWORD, (PTR) & m32r_cgen_opval_h_accums },
-/* end-sanitize-m32rx */
-/* start-sanitize-m32rx */
- { "h-abort", CGEN_ASM_KEYWORD, (PTR) 0 },
-/* end-sanitize-m32rx */
- { "h-cond", CGEN_ASM_KEYWORD, (PTR) 0 },
- { "h-sm", CGEN_ASM_KEYWORD, (PTR) 0 },
- { "h-bsm", CGEN_ASM_KEYWORD, (PTR) 0 },
- { "h-ie", CGEN_ASM_KEYWORD, (PTR) 0 },
- { "h-bie", CGEN_ASM_KEYWORD, (PTR) 0 },
- { "h-bcond", CGEN_ASM_KEYWORD, (PTR) 0 },
- { "h-bpc", CGEN_ASM_KEYWORD, (PTR) 0 },
- { 0 }
-};
-
-const CGEN_OPERAND m32r_cgen_operand_table[MAX_OPERANDS] =
-{
-/* pc: program counter */
- { "pc", 0, 0, { 0, 0|(1<<CGEN_OPERAND_FAKE)|(1<<CGEN_OPERAND_PC), { 0 } } },
-/* sr: source register */
- { "sr", 12, 4, { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
-/* dr: destination register */
- { "dr", 4, 4, { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
-/* src1: source register 1 */
- { "src1", 4, 4, { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
-/* src2: source register 2 */
- { "src2", 12, 4, { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
-/* scr: source control register */
- { "scr", 12, 4, { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
-/* dcr: destination control register */
- { "dcr", 4, 4, { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
-/* simm8: 8 bit signed immediate */
- { "simm8", 8, 8, { 0, 0, { 0 } } },
-/* simm16: 16 bit signed immediate */
- { "simm16", 16, 16, { 0, 0, { 0 } } },
-/* uimm4: 4 bit trap number */
- { "uimm4", 12, 4, { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
-/* uimm5: 5 bit shift count */
- { "uimm5", 11, 5, { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
-/* uimm16: 16 bit unsigned immediate */
- { "uimm16", 16, 16, { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
-/* start-sanitize-m32rx */
-/* accs: accumulator register */
- { "accs", 12, 2, { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
-/* end-sanitize-m32rx */
-/* start-sanitize-m32rx */
-/* acc: accumulator reg (d) */
- { "acc", 8, 1, { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
-/* end-sanitize-m32rx */
-/* hi16: high 16 bit immediate, sign optional */
- { "hi16", 16, 16, { 0, 0|(1<<CGEN_OPERAND_SIGN_OPT)|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
-/* slo16: 16 bit signed immediate, for low() */
- { "slo16", 16, 16, { 0, 0, { 0 } } },
-/* ulo16: 16 bit unsigned immediate, for low() */
- { "ulo16", 16, 16, { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
-/* uimm24: 24 bit address */
- { "uimm24", 8, 24, { 0, 0|(1<<CGEN_OPERAND_RELOC)|(1<<CGEN_OPERAND_ABS_ADDR)|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
-/* disp8: 8 bit displacement */
- { "disp8", 8, 8, { 0, 0|(1<<CGEN_OPERAND_RELAX)|(1<<CGEN_OPERAND_RELOC)|(1<<CGEN_OPERAND_PCREL_ADDR), { 0 } } },
-/* disp16: 16 bit displacement */
- { "disp16", 16, 16, { 0, 0|(1<<CGEN_OPERAND_RELOC)|(1<<CGEN_OPERAND_PCREL_ADDR), { 0 } } },
-/* disp24: 24 bit displacement */
- { "disp24", 8, 24, { 0, 0|(1<<CGEN_OPERAND_RELAX)|(1<<CGEN_OPERAND_RELOC)|(1<<CGEN_OPERAND_PCREL_ADDR), { 0 } } },
-/* condbit: condition bit */
- { "condbit", 0, 0, { 0, 0|(1<<CGEN_OPERAND_FAKE), { 0 } } },
-/* accum: accumulator */
- { "accum", 0, 0, { 0, 0|(1<<CGEN_OPERAND_FAKE), { 0 } } },
-/* start-sanitize-m32rx */
-/* abort-parallel-execution: abort parallel execution */
- { "abort-parallel-execution", 0, 0, { 0, 0|(1<<CGEN_OPERAND_FAKE), { 0 } } },
-/* end-sanitize-m32rx */
-};
-
-#define OP 1 /* syntax value for mnemonic */
-
-static const CGEN_SYNTAX syntax_table[] =
-{
-/* <op> $dr,$sr */
-/* 0 */ { OP, ' ', 130, ',', 129, 0 },
-/* <op> $dr,$sr,#$slo16 */
-/* 1 */ { OP, ' ', 130, ',', 129, ',', '#', 143, 0 },
-/* <op> $dr,$sr,$slo16 */
-/* 2 */ { OP, ' ', 130, ',', 129, ',', 143, 0 },
-/* <op> $dr,$sr,#$uimm16 */
-/* 3 */ { OP, ' ', 130, ',', 129, ',', '#', 139, 0 },
-/* <op> $dr,$sr,$uimm16 */
-/* 4 */ { OP, ' ', 130, ',', 129, ',', 139, 0 },
-/* <op> $dr,$sr,#$ulo16 */
-/* 5 */ { OP, ' ', 130, ',', 129, ',', '#', 144, 0 },
-/* <op> $dr,$sr,$ulo16 */
-/* 6 */ { OP, ' ', 130, ',', 129, ',', 144, 0 },
-/* <op> $dr,#$simm8 */
-/* 7 */ { OP, ' ', 130, ',', '#', 135, 0 },
-/* <op> $dr,$simm8 */
-/* 8 */ { OP, ' ', 130, ',', 135, 0 },
-/* <op> $dr,$sr,#$simm16 */
-/* 9 */ { OP, ' ', 130, ',', 129, ',', '#', 136, 0 },
-/* <op> $dr,$sr,$simm16 */
-/* 10 */ { OP, ' ', 130, ',', 129, ',', 136, 0 },
-/* <op> $disp8 */
-/* 11 */ { OP, ' ', 146, 0 },
-/* <op> $disp24 */
-/* 12 */ { OP, ' ', 148, 0 },
-/* <op> $src1,$src2,$disp16 */
-/* 13 */ { OP, ' ', 131, ',', 132, ',', 147, 0 },
-/* <op> $src2,$disp16 */
-/* 14 */ { OP, ' ', 132, ',', 147, 0 },
-/* <op> $src1,$src2 */
-/* 15 */ { OP, ' ', 131, ',', 132, 0 },
-/* <op> $src2,#$simm16 */
-/* 16 */ { OP, ' ', 132, ',', '#', 136, 0 },
-/* <op> $src2,$simm16 */
-/* 17 */ { OP, ' ', 132, ',', 136, 0 },
-/* <op> $src2,#$uimm16 */
-/* 18 */ { OP, ' ', 132, ',', '#', 139, 0 },
-/* <op> $src2,$uimm16 */
-/* 19 */ { OP, ' ', 132, ',', 139, 0 },
-/* <op> $src2 */
-/* 20 */ { OP, ' ', 132, 0 },
-/* <op> $sr */
-/* 21 */ { OP, ' ', 129, 0 },
-/* <op> $dr,@$sr */
-/* 22 */ { OP, ' ', 130, ',', '@', 129, 0 },
-/* <op> $dr,@($sr) */
-/* 23 */ { OP, ' ', 130, ',', '@', '(', 129, ')', 0 },
-/* <op> $dr,@($slo16,$sr) */
-/* 24 */ { OP, ' ', 130, ',', '@', '(', 143, ',', 129, ')', 0 },
-/* <op> $dr,@($sr,$slo16) */
-/* 25 */ { OP, ' ', 130, ',', '@', '(', 129, ',', 143, ')', 0 },
-/* <op> $dr,@$sr+ */
-/* 26 */ { OP, ' ', 130, ',', '@', 129, '+', 0 },
-/* <op> $dr,#$uimm24 */
-/* 27 */ { OP, ' ', 130, ',', '#', 145, 0 },
-/* <op> $dr,$uimm24 */
-/* 28 */ { OP, ' ', 130, ',', 145, 0 },
-/* <op> $dr,$slo16 */
-/* 29 */ { OP, ' ', 130, ',', 143, 0 },
-/* <op> $src1,$src2,$acc */
-/* 30 */ { OP, ' ', 131, ',', 132, ',', 141, 0 },
-/* <op> $dr */
-/* 31 */ { OP, ' ', 130, 0 },
-/* <op> $dr,$accs */
-/* 32 */ { OP, ' ', 130, ',', 140, 0 },
-/* <op> $dr,$scr */
-/* 33 */ { OP, ' ', 130, ',', 133, 0 },
-/* <op> $src1 */
-/* 34 */ { OP, ' ', 131, 0 },
-/* <op> $src1,$accs */
-/* 35 */ { OP, ' ', 131, ',', 140, 0 },
-/* <op> $sr,$dcr */
-/* 36 */ { OP, ' ', 129, ',', 134, 0 },
-/* <op> */
-/* 37 */ { OP, 0 },
-/* <op> $accs */
-/* 38 */ { OP, ' ', 140, 0 },
-/* <op> $dr,#$hi16 */
-/* 39 */ { OP, ' ', 130, ',', '#', 142, 0 },
-/* <op> $dr,$hi16 */
-/* 40 */ { OP, ' ', 130, ',', 142, 0 },
-/* <op> $dr,#$uimm5 */
-/* 41 */ { OP, ' ', 130, ',', '#', 138, 0 },
-/* <op> $dr,$uimm5 */
-/* 42 */ { OP, ' ', 130, ',', 138, 0 },
-/* <op> $src1,@$src2 */
-/* 43 */ { OP, ' ', 131, ',', '@', 132, 0 },
-/* <op> $src1,@($src2) */
-/* 44 */ { OP, ' ', 131, ',', '@', '(', 132, ')', 0 },
-/* <op> $src1,@($slo16,$src2) */
-/* 45 */ { OP, ' ', 131, ',', '@', '(', 143, ',', 132, ')', 0 },
-/* <op> $src1,@($src2,$slo16) */
-/* 46 */ { OP, ' ', 131, ',', '@', '(', 132, ',', 143, ')', 0 },
-/* <op> $src1,@+$src2 */
-/* 47 */ { OP, ' ', 131, ',', '@', '+', 132, 0 },
-/* <op> $src1,@-$src2 */
-/* 48 */ { OP, ' ', 131, ',', '@', '-', 132, 0 },
-/* <op> #$uimm4 */
-/* 49 */ { OP, ' ', '#', 137, 0 },
-/* <op> $uimm4 */
-/* 50 */ { OP, ' ', 137, 0 },
-/* <op> $dr,$src2 */
-/* 51 */ { OP, ' ', 130, ',', 132, 0 },