-/* Given symbol S, return m32r_cgen_<s>. */
-#define CGEN_SYM(s) CONCAT3 (m32r,_cgen_,s)
-
-/* Selected cpu families. */
-#define HAVE_CPU_M32R
-/* start-sanitize-m32rx */
-#define HAVE_CPU_M32RX
-/* end-sanitize-m32rx */
-
-#define CGEN_WORD_BITSIZE 32
-#define CGEN_DEFAULT_INSN_BITSIZE 32
-#define CGEN_BASE_INSN_BITSIZE 32
-#define CGEN_MAX_INSN_BITSIZE 32
-#define CGEN_DEFAULT_INSN_SIZE (CGEN_DEFAULT_INSN_BITSIZE / 8)
-#define CGEN_BASE_INSN_SIZE (CGEN_BASE_INSN_BITSIZE / 8)
-#define CGEN_MAX_INSN_SIZE (CGEN_MAX_INSN_BITSIZE / 8)
-#define CGEN_INT_INSN
-
-/* FIXME: Need to compute CGEN_MAX_SYNTAX_BYTES. */
-
-/* CGEN_MNEMONIC_OPERANDS is defined if mnemonics have operands.
- e.g. In "b,a foo" the ",a" is an operand. If mnemonics have operands
- we can't hash on everything up to the space. */
-#define CGEN_MNEMONIC_OPERANDS
-/* Maximum number of operands any insn or macro-insn has. */
-#define CGEN_MAX_INSN_OPERANDS 16
-
-/* Enums. */
-
-/* Enum declaration for insn format enums. */
-typedef enum insn_op1 {
- OP1_0, OP1_1, OP1_2, OP1_3
- , OP1_4, OP1_5, OP1_6, OP1_7
- , OP1_8, OP1_9, OP1_10, OP1_11
- , OP1_12, OP1_13, OP1_14, OP1_15
-} INSN_OP1;
-
-/* Enum declaration for op2 enums. */
-typedef enum insn_op2 {
- OP2_0, OP2_1, OP2_2, OP2_3
- , OP2_4, OP2_5, OP2_6, OP2_7
- , OP2_8, OP2_9, OP2_10, OP2_11
- , OP2_12, OP2_13, OP2_14, OP2_15
-} INSN_OP2;
-
-/* Enum declaration for general registers. */
-typedef enum h_gr {
- H_GR_FP = 13, H_GR_LR = 14, H_GR_SP = 15, H_GR_R0 = 0
- , H_GR_R1 = 1, H_GR_R2 = 2, H_GR_R3 = 3, H_GR_R4 = 4
- , H_GR_R5 = 5, H_GR_R6 = 6, H_GR_R7 = 7, H_GR_R8 = 8
- , H_GR_R9 = 9, H_GR_R10 = 10, H_GR_R11 = 11, H_GR_R12 = 12
- , H_GR_R13 = 13, H_GR_R14 = 14, H_GR_R15 = 15
-} H_GR;
-
-/* Enum declaration for control registers. */
-typedef enum h_cr {
- H_CR_PSW = 0, H_CR_CBR = 1, H_CR_SPI = 2, H_CR_SPU = 3
- , H_CR_BPC = 6, H_CR_CR0 = 0, H_CR_CR1 = 1, H_CR_CR2 = 2
- , H_CR_CR3 = 3, H_CR_CR4 = 4, H_CR_CR5 = 5, H_CR_CR6 = 6
- , H_CR_CR7 = 7, H_CR_CR8 = 8, H_CR_CR9 = 9, H_CR_CR10 = 10
- , H_CR_CR11 = 11, H_CR_CR12 = 12, H_CR_CR13 = 13, H_CR_CR14 = 14
- , H_CR_CR15 = 15
-} H_CR;
-
-/* start-sanitize-m32rx */
-/* Enum declaration for accumulators. */
-typedef enum h_accums {
- H_ACCUMS_A0, H_ACCUMS_A1
-} H_ACCUMS;
-
-/* end-sanitize-m32rx */
-/* Enum declaration for m32r operand types. */
-typedef enum cgen_operand_type {
- M32R_OPERAND_PC, M32R_OPERAND_SR, M32R_OPERAND_DR, M32R_OPERAND_SRC1
- , M32R_OPERAND_SRC2, M32R_OPERAND_SCR, M32R_OPERAND_DCR, M32R_OPERAND_SIMM8
- , M32R_OPERAND_SIMM16, M32R_OPERAND_UIMM4, M32R_OPERAND_UIMM5, M32R_OPERAND_UIMM16
-/* start-sanitize-m32rx */
- , M32R_OPERAND_IMM1
-/* end-sanitize-m32rx */
-/* start-sanitize-m32rx */
- , M32R_OPERAND_ACCD
-/* end-sanitize-m32rx */
-/* start-sanitize-m32rx */
- , M32R_OPERAND_ACCS
-/* end-sanitize-m32rx */
-/* start-sanitize-m32rx */
- , M32R_OPERAND_ACC
-/* end-sanitize-m32rx */
- , M32R_OPERAND_HASH, M32R_OPERAND_HI16, M32R_OPERAND_SLO16, M32R_OPERAND_ULO16
- , M32R_OPERAND_UIMM24, M32R_OPERAND_DISP8, M32R_OPERAND_DISP16, M32R_OPERAND_DISP24
- , M32R_OPERAND_CONDBIT, M32R_OPERAND_ACCUM, M32R_OPERAND_MAX
-} CGEN_OPERAND_TYPE;
-
-/* Non-boolean attributes. */
-
-/* Enum declaration for machine type selection. */
-typedef enum mach_attr {
- MACH_M32R
-/* start-sanitize-m32rx */
- , MACH_M32RX
-/* end-sanitize-m32rx */
- , MACH_MAX
-} MACH_ATTR;
-
-/* start-sanitize-m32rx */
-/* Enum declaration for parallel execution pipeline selection. */
-typedef enum pipe_attr {
- PIPE_NONE, PIPE_O, PIPE_S, PIPE_OS
-} PIPE_ATTR;
-
-/* end-sanitize-m32rx */
-/* Number of architecture variants. */
-#define MAX_MACHS ((int) MACH_MAX)
-
-/* Number of operands types. */
-#define MAX_OPERANDS ((int) M32R_OPERAND_MAX)
-
-/* Maximum number of operands referenced by any insn. */
-#define MAX_OPERAND_INSTANCES 8
-
-/* Operand and instruction attribute indices. */
-
-/* Enum declaration for cgen_operand attrs. */
-typedef enum cgen_operand_attr {
- CGEN_OPERAND_ABS_ADDR, CGEN_OPERAND_FAKE, CGEN_OPERAND_HASH_PREFIX, CGEN_OPERAND_NEGATIVE
- , CGEN_OPERAND_PC, CGEN_OPERAND_PCREL_ADDR, CGEN_OPERAND_RELAX, CGEN_OPERAND_RELOC
- , CGEN_OPERAND_SIGN_OPT, CGEN_OPERAND_UNSIGNED
-} CGEN_OPERAND_ATTR;
-
-/* Number of non-boolean elements in cgen_operand. */
-#define CGEN_OPERAND_NBOOL_ATTRS ((int) CGEN_OPERAND_ABS_ADDR)
-
-/* Enum declaration for cgen_insn attrs. */
-typedef enum cgen_insn_attr {
- CGEN_INSN_MACH
-/* start-sanitize-m32rx */
- , CGEN_INSN_PIPE
-/* end-sanitize-m32rx */
- , CGEN_INSN_ALIAS, CGEN_INSN_COND_CTI, CGEN_INSN_FILL_SLOT, CGEN_INSN_NO_DIS
- , CGEN_INSN_PARALLEL, CGEN_INSN_RELAX, CGEN_INSN_RELAXABLE, CGEN_INSN_SPECIAL
- , CGEN_INSN_UNCOND_CTI
-} CGEN_INSN_ATTR;