+ if ((dialect & PPC_OPCODE_RAW) == 0)
+ return opcode;
+
+ /* The raw machine insn is one that is not a specialization. */
+ if (last == NULL
+ || (last->mask & ~opcode->mask) != 0)
+ last = opcode;
+ }
+
+ return last;
+}
+
+/* Find a match for INSN in the VLE opcode table. */
+
+static const struct powerpc_opcode *
+lookup_vle (uint64_t insn)
+{
+ const struct powerpc_opcode *opcode;
+ const struct powerpc_opcode *opcode_end;
+ unsigned op, seg;
+
+ op = PPC_OP (insn);
+ if (op >= 0x20 && op <= 0x37)
+ {
+ /* This insn has a 4-bit opcode. */
+ op &= 0x3c;
+ }
+ seg = VLE_OP_TO_SEG (op);
+
+ /* Find the first match in the opcode table for this major opcode. */
+ opcode_end = vle_opcodes + vle_opcd_indices[seg + 1];
+ for (opcode = vle_opcodes + vle_opcd_indices[seg];
+ opcode < opcode_end;
+ ++opcode)
+ {
+ uint64_t table_opcd = opcode->opcode;
+ uint64_t table_mask = opcode->mask;
+ bfd_boolean table_op_is_short = PPC_OP_SE_VLE(table_mask);
+ uint64_t insn2;
+ const unsigned char *opindex;
+ const struct powerpc_operand *operand;
+ int invalid;
+
+ insn2 = insn;
+ if (table_op_is_short)
+ insn2 >>= 16;
+ if ((insn2 & table_mask) != table_opcd)
+ continue;
+
+ /* Check validity of operands. */
+ invalid = 0;
+ for (opindex = opcode->operands; *opindex != 0; ++opindex)
+ {
+ operand = powerpc_operands + *opindex;
+ if (operand->extract)
+ (*operand->extract) (insn, (ppc_cpu_t)0, &invalid);
+ }
+ if (invalid)
+ continue;
+
+ return opcode;
+ }
+
+ return NULL;
+}
+
+/* Find a match for INSN in the SPE2 opcode table. */
+
+static const struct powerpc_opcode *
+lookup_spe2 (uint64_t insn)
+{
+ const struct powerpc_opcode *opcode, *opcode_end;
+ unsigned op, xop, seg;
+
+ op = PPC_OP (insn);
+ if (op != 0x4)
+ {
+ /* This is not SPE2 insn.
+ * All SPE2 instructions have OP=4 and differs by XOP */
+ return NULL;
+ }
+ xop = SPE2_XOP (insn);
+ seg = SPE2_XOP_TO_SEG (xop);
+
+ /* Find the first match in the opcode table for this major opcode. */
+ opcode_end = spe2_opcodes + spe2_opcd_indices[seg + 1];
+ for (opcode = spe2_opcodes + spe2_opcd_indices[seg];
+ opcode < opcode_end;
+ ++opcode)
+ {
+ uint64_t table_opcd = opcode->opcode;
+ uint64_t table_mask = opcode->mask;
+ uint64_t insn2;
+ const unsigned char *opindex;
+ const struct powerpc_operand *operand;
+ int invalid;
+
+ insn2 = insn;
+ if ((insn2 & table_mask) != table_opcd)
+ continue;
+
+ /* Check validity of operands. */
+ invalid = 0;
+ for (opindex = opcode->operands; *opindex != 0; ++opindex)
+ {
+ operand = powerpc_operands + *opindex;
+ if (operand->extract)
+ (*operand->extract) (insn, (ppc_cpu_t)0, &invalid);
+ }
+ if (invalid)
+ continue;
+
+ return opcode;
+ }
+
+ return NULL;
+}
+
+/* Print a PowerPC or POWER instruction. */
+
+static int
+print_insn_powerpc (bfd_vma memaddr,
+ struct disassemble_info *info,
+ int bigendian,
+ ppc_cpu_t dialect)
+{
+ bfd_byte buffer[4];
+ int status;
+ uint64_t insn;
+ const struct powerpc_opcode *opcode;
+ int insn_length = 4; /* Assume we have a normal 4-byte instruction. */
+
+ status = (*info->read_memory_func) (memaddr, buffer, 4, info);
+
+ /* The final instruction may be a 2-byte VLE insn. */
+ if (status != 0 && (dialect & PPC_OPCODE_VLE) != 0)
+ {
+ /* Clear buffer so unused bytes will not have garbage in them. */
+ buffer[0] = buffer[1] = buffer[2] = buffer[3] = 0;
+ status = (*info->read_memory_func) (memaddr, buffer, 2, info);
+ }
+
+ if (status != 0)
+ {
+ (*info->memory_error_func) (status, memaddr, info);
+ return -1;
+ }
+
+ if (bigendian)
+ insn = bfd_getb32 (buffer);
+ else
+ insn = bfd_getl32 (buffer);
+
+ /* Get the major opcode of the insn. */
+ opcode = NULL;
+ if ((dialect & PPC_OPCODE_POWERXX) != 0
+ && PPC_OP (insn) == 0x1)
+ {
+ uint64_t temp_insn, suffix;
+ status = (*info->read_memory_func) (memaddr + 4, buffer, 4, info);
+ if (status == 0)
+ {
+ if (bigendian)
+ suffix = bfd_getb32 (buffer);
+ else
+ suffix = bfd_getl32 (buffer);
+ temp_insn = (insn << 32) | suffix;
+ opcode = lookup_prefix (temp_insn, dialect & ~PPC_OPCODE_ANY);
+ if (opcode == NULL && (dialect & PPC_OPCODE_ANY) != 0)
+ opcode = lookup_prefix (temp_insn, dialect);
+ if (opcode != NULL)
+ {
+ insn = temp_insn;
+ insn_length = 8;
+ if ((info->flags & WIDE_OUTPUT) != 0)
+ info->bytes_per_line = 8;
+ }
+ }
+ }
+ if (opcode == NULL && (dialect & PPC_OPCODE_VLE) != 0)
+ {
+ opcode = lookup_vle (insn);
+ if (opcode != NULL && PPC_OP_SE_VLE (opcode->mask))
+ {
+ /* The operands will be fetched out of the 16-bit instruction. */
+ insn >>= 16;
+ insn_length = 2;
+ }
+ }
+ if (opcode == NULL && (dialect & PPC_OPCODE_SPE2) != 0)
+ opcode = lookup_spe2 (insn);
+ if (opcode == NULL)
+ opcode = lookup_powerpc (insn, dialect & ~PPC_OPCODE_ANY);
+ if (opcode == NULL && (dialect & PPC_OPCODE_ANY) != 0)
+ opcode = lookup_powerpc (insn, dialect);
+
+ if (opcode != NULL)
+ {
+ const unsigned char *opindex;
+ const struct powerpc_operand *operand;
+ enum {
+ need_comma = 0,
+ need_1space = 1,
+ need_2spaces = 2,
+ need_3spaces = 3,
+ need_4spaces = 4,
+ need_5spaces = 5,
+ need_6spaces = 6,
+ need_7spaces = 7,
+ need_paren
+ } op_separator;
+ bfd_boolean skip_optional;
+ int blanks;
+
+ (*info->fprintf_func) (info->stream, "%s", opcode->name);
+ /* gdb fprintf_func doesn't return count printed. */
+ blanks = 8 - strlen (opcode->name);
+ if (blanks <= 0)
+ blanks = 1;