+ else if (operand->flags & S390_OPERAND_VR)
+ {
+ /* Extract the extra bits for a vector register operand stored
+ in the RXB field. */
+ unsigned vr = operand->shift == 32 ? 3
+ : (unsigned) operand->shift / 4 - 2;
+
+ ret.u = val | ((orig_insn[4] & (1 << (3 - vr))) << (vr + 1));
+ }
+ else
+ ret.u = val;
+
+ return ret;
+}
+
+/* Print the S390 instruction in BUFFER, assuming that it matches the
+ given OPCODE. */
+
+static void
+s390_print_insn_with_opcode (bfd_vma memaddr,
+ struct disassemble_info *info,
+ const bfd_byte *buffer,
+ const struct s390_opcode *opcode)
+{
+ const unsigned char *opindex;
+ char separator;
+
+ /* Mnemonic. */
+ info->fprintf_func (info->stream, "%s", opcode->name);
+
+ /* Operands. */
+ separator = '\t';
+ for (opindex = opcode->operands; *opindex != 0; opindex++)
+ {
+ const struct s390_operand *operand = s390_operands + *opindex;
+ union operand_value val = s390_extract_operand (buffer, operand);
+ unsigned long flags = operand->flags;
+
+ if ((flags & S390_OPERAND_INDEX) && val.u == 0)
+ continue;
+ if ((flags & S390_OPERAND_BASE) &&
+ val.u == 0 && separator == '(')
+ {
+ separator = ',';
+ continue;
+ }
+
+ /* For instructions with a last optional operand don't print it
+ if zero. */
+ if ((opcode->flags & (S390_INSTR_FLAG_OPTPARM | S390_INSTR_FLAG_OPTPARM2))
+ && val.u == 0
+ && opindex[1] == 0)
+ break;
+
+ if ((opcode->flags & S390_INSTR_FLAG_OPTPARM2)
+ && val.u == 0 && opindex[1] != 0 && opindex[2] == 0)
+ {
+ union operand_value next_op_val =
+ s390_extract_operand (buffer, s390_operands + opindex[1]);
+ if (next_op_val.u == 0)
+ break;
+ }
+
+ if (flags & S390_OPERAND_GPR)
+ info->fprintf_func (info->stream, "%c%%r%u", separator, val.u);
+ else if (flags & S390_OPERAND_FPR)
+ info->fprintf_func (info->stream, "%c%%f%u", separator, val.u);
+ else if (flags & S390_OPERAND_VR)
+ info->fprintf_func (info->stream, "%c%%v%i", separator, val.u);
+ else if (flags & S390_OPERAND_AR)
+ info->fprintf_func (info->stream, "%c%%a%u", separator, val.u);
+ else if (flags & S390_OPERAND_CR)
+ info->fprintf_func (info->stream, "%c%%c%u", separator, val.u);
+ else if (flags & S390_OPERAND_PCREL)
+ {
+ info->fprintf_func (info->stream, "%c", separator);
+ info->print_address_func (memaddr + val.i + val.i, info);
+ }
+ else if (flags & S390_OPERAND_SIGNED)
+ info->fprintf_func (info->stream, "%c%i", separator, val.i);
+ else
+ {
+ if (flags & S390_OPERAND_OR1)
+ val.u &= ~1;
+ if (flags & S390_OPERAND_OR2)
+ val.u &= ~2;
+ if (flags & S390_OPERAND_OR8)
+ val.u &= ~8;
+
+ if ((opcode->flags & S390_INSTR_FLAG_OPTPARM)
+ && val.u == 0
+ && opindex[1] == 0)
+ break;
+ info->fprintf_func (info->stream, "%c%u", separator, val.u);
+ }
+
+ if (flags & S390_OPERAND_DISP)
+ separator = '(';
+ else if (flags & S390_OPERAND_BASE)
+ {
+ info->fprintf_func (info->stream, ")");
+ separator = ',';
+ }
+ else
+ separator = ',';
+ }
+}
+
+/* Check whether opcode A's mask is more specific than that of B. */
+
+static int
+opcode_mask_more_specific (const struct s390_opcode *a,
+ const struct s390_opcode *b)
+{
+ return (((int) a->mask[0] + a->mask[1] + a->mask[2]
+ + a->mask[3] + a->mask[4] + a->mask[5])
+ > ((int) b->mask[0] + b->mask[1] + b->mask[2]
+ + b->mask[3] + b->mask[4] + b->mask[5]));