-/* FIXME--need to deal with byte order (probably using masking and
- shifting rather than bitfields is easiest). */
-
-union sparc_insn
- {
- unsigned long int code;
- struct
- {
- unsigned int anop:2;
-#define op ldst.anop
- unsigned int anrd:5;
-#define rd ldst.anrd
- unsigned int op3:6;
- unsigned int anrs1:5;
-#define rs1 ldst.anrs1
- unsigned int i:1;
- unsigned int anasi:8;
-#define asi ldst.anasi
- unsigned int anrs2:5;
-#define rs2 ldst.anrs2
-#define shcnt rs2
- } ldst;
- struct
- {
- unsigned int anop:2, anrd:5, op3:6, anrs1:5, i:1;
- unsigned int IMM13:13;
-#define imm13 IMM13.IMM13
- } IMM13;
- struct
- {
- unsigned int anop:2;
- unsigned int a:1;
- unsigned int cond:4;
- unsigned int op2:3;
- unsigned int DISP22:22;
-#define disp22 branch.DISP22
- } branch;
-#ifndef NO_V9
- struct
- {
- unsigned int _OP:2, _RD:5, op3:6, _RS1:5;
- unsigned int DISP14:14;
-#define disp14 DISP14.DISP14
- } DISP14;
- struct
- {
- unsigned int _OP:2;
- unsigned int a:1;
- unsigned int cond:4;
- unsigned int op2:3;
- unsigned int p:1;
- unsigned int DISP21:21;
-#define disp21 branch2.DISP21
- } branch2;
-#endif /* NO_V9 */
-
-#define imm22 disp22
- struct
- {
- unsigned int anop:2;
- unsigned int adisp30:30;
-#define disp30 call.adisp30
- } call;
- };
+/* These are ordered according to there register number in
+ rdpr and wrpr insns. */
+static char *v9_priv_reg_names[] =
+{
+ "tpc", "tnpc", "tstate", "tt", "tick", "tba", "pstate", "tl",
+ "pil", "cwp", "cansave", "canrestore", "cleanwin", "otherwin",
+ "wstate", "fq"
+ /* "ver" - special cased */
+};
+
+/* These are ordered according to there register number in
+ rd and wr insns (-16). */
+static char *v9a_asr_reg_names[] =
+{
+ "pcr", "pic", "dcr", "gsr", "set_softint", "clear_softint",
+ "softint", "tick_cmpr", "sys_tick", "sys_tick_cmpr"
+};
+
+/* Macros used to extract instruction fields. Not all fields have
+ macros defined here, only those which are actually used. */
+
+#define X_RD(i) (((i) >> 25) & 0x1f)
+#define X_RS1(i) (((i) >> 14) & 0x1f)
+#define X_LDST_I(i) (((i) >> 13) & 1)
+#define X_ASI(i) (((i) >> 5) & 0xff)
+#define X_RS2(i) (((i) >> 0) & 0x1f)
+#define X_IMM(i,n) (((i) >> 0) & ((1 << (n)) - 1))
+#define X_SIMM(i,n) SEX (X_IMM ((i), (n)), (n))
+#define X_DISP22(i) (((i) >> 0) & 0x3fffff)
+#define X_IMM22(i) X_DISP22 (i)
+#define X_DISP30(i) (((i) >> 0) & 0x3fffffff)
+
+/* These are for v9. */
+#define X_DISP16(i) (((((i) >> 20) & 3) << 14) | (((i) >> 0) & 0x3fff))
+#define X_DISP19(i) (((i) >> 0) & 0x7ffff)
+#define X_MEMBAR(i) ((i) & 0x7f)
+
+/* Here is the union which was used to extract instruction fields
+ before the shift and mask macros were written.
+
+ union sparc_insn
+ {
+ unsigned long int code;
+ struct
+ {
+ unsigned int anop:2;
+ #define op ldst.anop
+ unsigned int anrd:5;
+ #define rd ldst.anrd
+ unsigned int op3:6;
+ unsigned int anrs1:5;
+ #define rs1 ldst.anrs1
+ unsigned int i:1;
+ unsigned int anasi:8;
+ #define asi ldst.anasi
+ unsigned int anrs2:5;
+ #define rs2 ldst.anrs2
+ #define shcnt rs2
+ } ldst;
+ struct
+ {
+ unsigned int anop:2, anrd:5, op3:6, anrs1:5, i:1;
+ unsigned int IMM13:13;
+ #define imm13 IMM13.IMM13
+ } IMM13;
+ struct
+ {
+ unsigned int anop:2;
+ unsigned int a:1;
+ unsigned int cond:4;
+ unsigned int op2:3;
+ unsigned int DISP22:22;
+ #define disp22 branch.DISP22
+ #define imm22 disp22
+ } branch;
+ struct
+ {
+ unsigned int anop:2;
+ unsigned int a:1;
+ unsigned int z:1;
+ unsigned int rcond:3;
+ unsigned int op2:3;
+ unsigned int DISP16HI:2;
+ unsigned int p:1;
+ unsigned int _rs1:5;
+ unsigned int DISP16LO:14;
+ } branch16;
+ struct
+ {
+ unsigned int anop:2;
+ unsigned int adisp30:30;
+ #define disp30 call.adisp30
+ } call;
+ };
+
+ */