+/* Handle ASI's. */
+
+static sparc_asi asi_table[] =
+{
+ /* These are in the v9 architecture manual. */
+ /* The shorter versions appear first, they're here because Sun's as has them.
+ Sun's as uses #ASI_P_L instead of #ASI_PL (which appears in the
+ UltraSPARC architecture manual). */
+ { 0x04, "#ASI_N", v9 },
+ { 0x0c, "#ASI_N_L", v9 },
+ { 0x10, "#ASI_AIUP", v9 },
+ { 0x11, "#ASI_AIUS", v9 },
+ { 0x18, "#ASI_AIUP_L", v9 },
+ { 0x19, "#ASI_AIUS_L", v9 },
+ { 0x80, "#ASI_P", v9 },
+ { 0x81, "#ASI_S", v9 },
+ { 0x82, "#ASI_PNF", v9 },
+ { 0x83, "#ASI_SNF", v9 },
+ { 0x88, "#ASI_P_L", v9 },
+ { 0x89, "#ASI_S_L", v9 },
+ { 0x8a, "#ASI_PNF_L", v9 },
+ { 0x8b, "#ASI_SNF_L", v9 },
+ { 0x04, "#ASI_NUCLEUS", v9 },
+ { 0x0c, "#ASI_NUCLEUS_LITTLE", v9 },
+ { 0x10, "#ASI_AS_IF_USER_PRIMARY", v9 },
+ { 0x11, "#ASI_AS_IF_USER_SECONDARY", v9 },
+ { 0x18, "#ASI_AS_IF_USER_PRIMARY_LITTLE", v9 },
+ { 0x19, "#ASI_AS_IF_USER_SECONDARY_LITTLE", v9 },
+ { 0x80, "#ASI_PRIMARY", v9 },
+ { 0x81, "#ASI_SECONDARY", v9 },
+ { 0x82, "#ASI_PRIMARY_NOFAULT", v9 },
+ { 0x83, "#ASI_SECONDARY_NOFAULT", v9 },
+ { 0x88, "#ASI_PRIMARY_LITTLE", v9 },
+ { 0x89, "#ASI_SECONDARY_LITTLE", v9 },
+ { 0x8a, "#ASI_PRIMARY_NOFAULT_LITTLE", v9 },
+ { 0x8b, "#ASI_SECONDARY_NOFAULT_LITTLE", v9 },
+ /* These are UltraSPARC and Niagara extensions. */
+ { 0x14, "#ASI_PHYS_USE_EC", v9b },
+ { 0x15, "#ASI_PHYS_BYPASS_EC_E", v9b },
+ { 0x16, "#ASI_BLK_AIUP_4V", v9c },
+ { 0x17, "#ASI_BLK_AIUS_4V", v9c },
+ { 0x1c, "#ASI_PHYS_USE_EC_L", v9b },
+ { 0x1d, "#ASI_PHYS_BYPASS_EC_E_L", v9b },
+ { 0x1e, "#ASI_BLK_AIUP_L_4V", v9c },
+ { 0x1f, "#ASI_BLK_AIUS_L_4V", v9c },
+ { 0x20, "#ASI_SCRATCHPAD", v9c },
+ { 0x21, "#ASI_MMU", v9c },
+ { 0x23, "#ASI_BLK_INIT_QUAD_LDD_AIUS", v9c },
+ { 0x24, "#ASI_NUCLEUS_QUAD_LDD", v9b },
+ { 0x24, "#ASI_CORE_COMMIT_COUNT", m8 },
+ { 0x24, "#ASI_CORE_SELECT_COUNT", m8 },
+ { 0x25, "#ASI_QUEUE", v9c },
+ { 0x26, "#ASI_QUAD_LDD_PHYS_4V", v9c },
+ { 0x2c, "#ASI_NUCLEUS_QUAD_LDD_L", v9b },
+ { 0x30, "#ASI_PCACHE_DATA_STATUS", v9b },
+ { 0x31, "#ASI_PCACHE_DATA", v9b },
+ { 0x32, "#ASI_PCACHE_TAG", v9b },
+ { 0x33, "#ASI_PCACHE_SNOOP_TAG", v9b },
+ { 0x34, "#ASI_QUAD_LDD_PHYS", v9b },
+ { 0x38, "#ASI_WCACHE_VALID_BITS", v9b },
+ { 0x39, "#ASI_WCACHE_DATA", v9b },
+ { 0x3a, "#ASI_WCACHE_TAG", v9b },
+ { 0x3b, "#ASI_WCACHE_SNOOP_TAG", v9b },
+ { 0x3c, "#ASI_QUAD_LDD_PHYS_L", v9b },
+ { 0x40, "#ASI_SRAM_FAST_INIT", v9b },
+ { 0x41, "#ASI_CORE_AVAILABLE", v9b },
+ { 0x41, "#ASI_CORE_ENABLE_STAT", v9b },
+ { 0x41, "#ASI_CORE_ENABLE", v9b },
+ { 0x41, "#ASI_XIR_STEERING", v9b },
+ { 0x41, "#ASI_CORE_RUNNING_RW", v9b },
+ { 0x41, "#ASI_CORE_RUNNING_W1S", v9b },
+ { 0x41, "#ASI_CORE_RUNNING_W1C", v9b },
+ { 0x41, "#ASI_CORE_RUNNING_STAT", v9b },
+ { 0x41, "#ASI_CMT_ERROR_STEERING", v9b },
+ { 0x45, "#ASI_LSU_CONTROL_REG", v9b },
+ { 0x45, "#ASI_DCU_CONTROL_REG", v9b },
+ { 0x46, "#ASI_DCACHE_DATA", v9b },
+ { 0x47, "#ASI_DCACHE_TAG", v9b },
+ { 0x48, "#ASI_INTR_DISPATCH_STAT", v9b },
+ { 0x49, "#ASI_INTR_RECEIVE", v9b },
+ { 0x4b, "#ASI_ESTATE_ERROR_EN", v9b },
+ { 0x4c, "#ASI_AFSR", v9b },
+ { 0x4d, "#ASI_AFAR", v9b },
+ { 0x4e, "#ASI_EC_TAG_DATA", v9b },
+ { 0x48, "#ASI_ARF_ECC_REG", m8 },
+ { 0x50, "#ASI_IMMU", v9b },
+ { 0x51, "#ASI_IMMU_TSB_8KB_PTR", v9b },
+ { 0x52, "#ASI_IMMU_TSB_64KB_PTR", v9b },
+ { 0x53, "#ASI_ITLB_PROBE", m8 },
+ { 0x54, "#ASI_ITLB_DATA_IN", v9b },
+ { 0x55, "#ASI_ITLB_DATA_ACCESS", v9b },
+ { 0x56, "#ASI_ITLB_TAG_READ", v9b },
+ { 0x57, "#ASI_IMMU_DEMAP", v9b },
+ { 0x58, "#ASI_DMMU", v9b },
+ { 0x58, "#ASI_DSFAR", m8 },
+ { 0x59, "#ASI_DMMU_TSB_8KB_PTR", v9b },
+ { 0x5a, "#ASI_DMMU_TSB_64KB_PTR", v9b },
+ { 0x5a, "#ASI_DTLB_PROBE_PRIMARY", m8 },
+ { 0x5b, "#ASI_DMMU_TSB_DIRECT_PTR", v9b },
+ { 0x5b, "#ASI_DTLB_PROBE_REAL", m8 },
+ { 0x5c, "#ASI_DTLB_DATA_IN", v9b },
+ { 0x5d, "#ASI_DTLB_DATA_ACCESS", v9b },
+ { 0x5e, "#ASI_DTLB_TAG_READ", v9b },
+ { 0x5f, "#ASI_DMMU_DEMAP", v9b },
+ { 0x60, "#ASI_IIU_INST_TRAP", v9b },
+ { 0x63, "#ASI_INTR_ID", v9b },
+ { 0x63, "#ASI_CORE_ID", v9b },
+ { 0x63, "#ASI_CESR_ID", v9b },
+ { 0x64, "#ASI_CORE_SELECT_COMMIT_NHT", m8 },
+ { 0x66, "#ASI_IC_INSTR", v9b },
+ { 0x67, "#ASI_IC_TAG", v9b },
+ { 0x68, "#ASI_IC_STAG", v9b },
+ { 0x6f, "#ASI_BRPRED_ARRAY", v9b },
+ { 0x70, "#ASI_BLK_AIUP", v9b },
+ { 0x71, "#ASI_BLK_AIUS", v9b },
+ { 0x72, "#ASI_MCU_CTRL_REG", v9b },
+ { 0x74, "#ASI_EC_DATA", v9b },
+ { 0x75, "#ASI_EC_CTRL", v9b },
+ { 0x76, "#ASI_EC_W", v9b },
+ { 0x77, "#ASI_INTR_W", v9b },
+ { 0x77, "#ASI_INTR_DATAN_W", v9b },
+ { 0x77, "#ASI_INTR_DISPATCH_W", v9b },
+ { 0x78, "#ASI_BLK_AIUPL", v9b },
+ { 0x79, "#ASI_BLK_AIUSL", v9b },
+ { 0x7e, "#ASI_EC_R", v9b },
+ { 0x7f, "#ASI_INTR_R", v9b },
+ { 0x7f, "#ASI_INTR_DATAN_R", v9b },
+ { 0xc0, "#ASI_PST8_P", v9b },
+ { 0xc1, "#ASI_PST8_S", v9b },
+ { 0xc2, "#ASI_PST16_P", v9b },
+ { 0xc3, "#ASI_PST16_S", v9b },
+ { 0xc4, "#ASI_PST32_P", v9b },
+ { 0xc5, "#ASI_PST32_S", v9b },
+ { 0xc8, "#ASI_PST8_PL", v9b },
+ { 0xc9, "#ASI_PST8_SL", v9b },
+ { 0xca, "#ASI_PST16_PL", v9b },
+ { 0xcb, "#ASI_PST16_SL", v9b },
+ { 0xcc, "#ASI_PST32_PL", v9b },
+ { 0xcd, "#ASI_PST32_SL", v9b },
+ { 0xd0, "#ASI_FL8_P", v9b },
+ { 0xd1, "#ASI_FL8_S", v9b },
+ { 0xd2, "#ASI_FL16_P", v9b },
+ { 0xd3, "#ASI_FL16_S", v9b },
+ { 0xd8, "#ASI_FL8_PL", v9b },
+ { 0xd9, "#ASI_FL8_SL", v9b },
+ { 0xda, "#ASI_FL16_PL", v9b },
+ { 0xdb, "#ASI_FL16_SL", v9b },
+ { 0xe0, "#ASI_BLK_COMMIT_P", v9b },
+ { 0xe1, "#ASI_BLK_COMMIT_S", v9b },
+ { 0xe2, "#ASI_BLK_INIT_QUAD_LDD_P", v9b },
+ { 0xf0, "#ASI_BLK_P", v9b },
+ { 0xf1, "#ASI_BLK_S", v9b },
+ { 0xf8, "#ASI_BLK_PL", v9b },
+ { 0xf9, "#ASI_BLK_SL", v9b },
+ { 0x22, "#ASI_TWINX_AIUP", v9c },
+ { 0x23, "#ASI_TWINX_AIUS", v9c },
+ { 0x26, "#ASI_TWINX_REAL", v9c },
+ { 0x27, "#ASI_TWINX_N", v9c },
+ { 0x2A, "#ASI_TWINX_AIUP_L", v9c },
+ { 0x2B, "#ASI_TWINX_AIUS_L", v9c },
+ { 0x2E, "#ASI_TWINX_REAL_L", v9c },
+ { 0x2F, "#ASI_TWINX_NL", v9c },
+ { 0xE2, "#ASI_TWINX_P", v9c },
+ { 0xE3, "#ASI_TWINX_S", v9c },
+ { 0xEA, "#ASI_TWINX_PL", v9c },
+ { 0xEB, "#ASI_TWINX_SL", v9c },
+ /* These are ASIs from UA2005, UA2007, OSA2011, & OSA 2015 */
+ { 0x12, "#ASI_MAIUP", v9m },
+ { 0x13, "#ASI_MAIUS", v9m },
+ { 0x14, "#ASI_REAL", v9c },
+ { 0x15, "#ASI_REAL_IO", v9c },
+ { 0x1c, "#ASI_REAL_L", v9c },
+ { 0x1d, "#ASI_REAL_IO_L", v9c },
+ { 0x30, "#ASI_AIPP", v9d },
+ { 0x31, "#ASI_AIPS", v9d },
+ { 0x36, "#ASI_AIPN", v9d },
+ { 0x38, "#ASI_AIPP_L", v9d },
+ { 0x39, "#ASI_AIPS_L", v9d },
+ { 0x3e, "#ASI_AIPN_L", v9d },
+ { 0x42, "#ASI_INST_MASK_REG", v9d },
+ { 0x42, "#ASI_LSU_DIAG_REG", v9d },
+ { 0x43, "#ASI_ERROR_INJECT_REG", v9d },
+ { 0x48, "#ASI_IRF_ECC_REG", v9d },
+ { 0x49, "#ASI_FRF_ECC_REG", v9d },
+ { 0x4e, "#ASI_SPARC_PWR_MGMT", v9d },
+ { 0x4f, "#ASI_HYP_SCRATCHPAD", v9c },
+ { 0x59, "#ASI_SCRATCHPAD_ACCESS", v9d },
+ { 0x5a, "#ASI_TICK_ACCESS", v9d },
+ { 0x5b, "#ASI_TSA_ACCESS", v9d },
+ { 0xb0, "#ASI_PIC", v9e },
+ { 0xf2, "#ASI_STBI_PM", v9e },
+ { 0xf3, "#ASI_STBI_SM", v9e },
+ { 0xfa, "#ASI_STBI_PLM", v9e },
+ { 0xfb, "#ASI_STBI_SLM", v9e },
+ { 0, 0, 0 }
+};
+
+/* Return the a pointer to the matching sparc_asi struct, NULL if not found. */
+
+const sparc_asi *
+sparc_encode_asi (const char *name)
+{
+ const sparc_asi *p;
+
+ for (p = asi_table; p->name; ++p)
+ if (strcmp (name, p->name) == 0)
+ return p;
+
+ return NULL;
+}
+
+/* Return the name for ASI value VALUE or NULL if not found. */
+
+const char *
+sparc_decode_asi (int value)
+{
+ const sparc_asi *p;
+
+ for (p = asi_table; p->name; ++p)
+ if (value == p->value)
+ return p->name;
+
+ return NULL;
+}
+\f