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Add multi-target tests
[deliverable/binutils-gdb.git]
/
opcodes
/
xc16x-asm.c
diff --git
a/opcodes/xc16x-asm.c
b/opcodes/xc16x-asm.c
index c7903e1f707ad8d63d57f64645900815a32f4898..a95a6fc4a9ba4b6d4d3f47fcf551c60e9f8e916f 100644
(file)
--- a/
opcodes/xc16x-asm.c
+++ b/
opcodes/xc16x-asm.c
@@
-1,11
+1,11
@@
+/* DO NOT EDIT! -*- buffer-read-only: t -*- vi:set ro: */
/* Assembler interface for targets using CGEN. -*- C -*-
CGEN: Cpu tools GENerator
THIS FILE IS MACHINE GENERATED WITH CGEN.
- the resultant file is machine generated, cgen-asm.in isn't
/* Assembler interface for targets using CGEN. -*- C -*-
CGEN: Cpu tools GENerator
THIS FILE IS MACHINE GENERATED WITH CGEN.
- the resultant file is machine generated, cgen-asm.in isn't
- Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2005, 2007, 2008, 2010
- Free Software Foundation, Inc.
+ Copyright (C) 1996-2020 Free Software Foundation, Inc.
This file is part of libopcodes.
This file is part of libopcodes.
@@
-95,7
+95,7
@@
parse_pof (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
*strp += 4;
return NULL;
}
*strp += 4;
return NULL;
}
- return _("Missing 'pof:' prefix");
+ return _("Missing 'pof:' prefix");
}
/* Handle 'pag:' prefixes (i.e. skip over them). */
}
/* Handle 'pag:' prefixes (i.e. skip over them). */
@@
-373,14
+373,16
@@
xc16x_cgen_parse_operand (CGEN_CPU_DESC cd,
default :
/* xgettext:c-format */
default :
/* xgettext:c-format */
- fprintf (stderr, _("Unrecognized field %d while parsing.\n"), opindex);
+ opcodes_error_handler
+ (_("internal error: unrecognized field %d while parsing"),
+ opindex);
abort ();
}
return errmsg;
}
abort ();
}
return errmsg;
}
-cgen_parse_fn * const xc16x_cgen_parse_handlers[] =
+cgen_parse_fn * const xc16x_cgen_parse_handlers[] =
{
parse_insn_normal,
};
{
parse_insn_normal,
};
@@
-410,9
+412,9
@@
CGEN_ASM_INIT_HOOK
Returns NULL for success, an error message for failure. */
Returns NULL for success, an error message for failure. */
-char *
+char *
xc16x_cgen_build_insn_regex (CGEN_INSN *insn)
xc16x_cgen_build_insn_regex (CGEN_INSN *insn)
-{
+{
CGEN_OPCODE *opc = (CGEN_OPCODE *) CGEN_INSN_OPCODE (insn);
const char *mnem = CGEN_INSN_MNEMONIC (insn);
char rxbuf[CGEN_MAX_RX_ELEMENTS];
CGEN_OPCODE *opc = (CGEN_OPCODE *) CGEN_INSN_OPCODE (insn);
const char *mnem = CGEN_INSN_MNEMONIC (insn);
char rxbuf[CGEN_MAX_RX_ELEMENTS];
@@
-451,18
+453,18
@@
xc16x_cgen_build_insn_regex (CGEN_INSN *insn)
/* Copy any remaining literals from the syntax string into the rx. */
for(; * syn != 0 && rx <= rxbuf + (CGEN_MAX_RX_ELEMENTS - 7 - 4); ++syn)
{
/* Copy any remaining literals from the syntax string into the rx. */
for(; * syn != 0 && rx <= rxbuf + (CGEN_MAX_RX_ELEMENTS - 7 - 4); ++syn)
{
- if (CGEN_SYNTAX_CHAR_P (* syn))
+ if (CGEN_SYNTAX_CHAR_P (* syn))
{
char c = CGEN_SYNTAX_CHAR (* syn);
{
char c = CGEN_SYNTAX_CHAR (* syn);
- switch (c)
+ switch (c)
{
/* Escape any regex metacharacters in the syntax. */
{
/* Escape any regex metacharacters in the syntax. */
- case '.': case '[': case '\\':
- case '*': case '^': case '$':
+ case '.': case '[': case '\\':
+ case '*': case '^': case '$':
#ifdef CGEN_ESCAPE_EXTENDED_REGEX
#ifdef CGEN_ESCAPE_EXTENDED_REGEX
- case '?': case '{': case '}':
+ case '?': case '{': case '}':
case '(': case ')': case '*':
case '|': case '+': case ']':
#endif
case '(': case ')': case '*':
case '|': case '+': case ']':
#endif
@@
-492,20
+494,20
@@
xc16x_cgen_build_insn_regex (CGEN_INSN *insn)
}
/* Trailing whitespace ok. */
}
/* Trailing whitespace ok. */
- * rx++ = '[';
- * rx++ = ' ';
- * rx++ = '\t';
- * rx++ = ']';
- * rx++ = '*';
+ * rx++ = '[';
+ * rx++ = ' ';
+ * rx++ = '\t';
+ * rx++ = ']';
+ * rx++ = '*';
/* But anchor it after that. */
/* But anchor it after that. */
- * rx++ = '$';
+ * rx++ = '$';
* rx = '\0';
CGEN_INSN_RX (insn) = xmalloc (sizeof (regex_t));
reg_err = regcomp ((regex_t *) CGEN_INSN_RX (insn), rxbuf, REG_NOSUB);
* rx = '\0';
CGEN_INSN_RX (insn) = xmalloc (sizeof (regex_t));
reg_err = regcomp ((regex_t *) CGEN_INSN_RX (insn), rxbuf, REG_NOSUB);
- if (reg_err == 0)
+ if (reg_err == 0)
return NULL;
else
{
return NULL;
else
{
@@
-704,7
+706,7
@@
xc16x_cgen_assemble_insn (CGEN_CPU_DESC cd,
const CGEN_INSN *insn = ilist->insn;
recognized_mnemonic = 1;
const CGEN_INSN *insn = ilist->insn;
recognized_mnemonic = 1;
-#ifdef CGEN_VALIDATE_INSN_SUPPORTED
+#ifdef CGEN_VALIDATE_INSN_SUPPORTED
/* Not usually needed as unsupported opcodes
shouldn't be in the hash lists. */
/* Is this insn supported by the selected cpu? */
/* Not usually needed as unsupported opcodes
shouldn't be in the hash lists. */
/* Is this insn supported by the selected cpu? */
@@
-764,7
+766,7
@@
xc16x_cgen_assemble_insn (CGEN_CPU_DESC cd,
if (strlen (start) > 50)
/* xgettext:c-format */
sprintf (errbuf, "%s `%.50s...'", tmp_errmsg, start);
if (strlen (start) > 50)
/* xgettext:c-format */
sprintf (errbuf, "%s `%.50s...'", tmp_errmsg, start);
- else
+ else
/* xgettext:c-format */
sprintf (errbuf, "%s `%.50s'", tmp_errmsg, start);
}
/* xgettext:c-format */
sprintf (errbuf, "%s `%.50s'", tmp_errmsg, start);
}
@@
-773,11
+775,11
@@
xc16x_cgen_assemble_insn (CGEN_CPU_DESC cd,
if (strlen (start) > 50)
/* xgettext:c-format */
sprintf (errbuf, _("bad instruction `%.50s...'"), start);
if (strlen (start) > 50)
/* xgettext:c-format */
sprintf (errbuf, _("bad instruction `%.50s...'"), start);
- else
+ else
/* xgettext:c-format */
sprintf (errbuf, _("bad instruction `%.50s'"), start);
}
/* xgettext:c-format */
sprintf (errbuf, _("bad instruction `%.50s'"), start);
}
-
+
*errmsg = errbuf;
return NULL;
}
*errmsg = errbuf;
return NULL;
}
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