+\f
+/* Disassembly support. */
+
+/* sprintf to a "stream" */
+
+int
+sim_disasm_sprintf VPARAMS ((SFILE *f, const char *format, ...))
+{
+#ifndef __STDC__
+ SFILE *f;
+ const char *format;
+#endif
+ int n;
+ va_list args;
+
+ VA_START (args, format);
+#ifndef __STDC__
+ f = va_arg (args, SFILE *);
+ format = va_arg (args, char *);
+#endif
+ vsprintf (f->current, format, args);
+ f->current += n = strlen (f->current);
+ va_end (args);
+ return n;
+}
+
+/* Memory read support for an opcodes disassembler. */
+
+int
+sim_disasm_read_memory (bfd_vma memaddr, bfd_byte *myaddr, int length,
+ struct disassemble_info *info)
+{
+ SIM_CPU *cpu = (SIM_CPU *) info->application_data;
+ SIM_DESC sd = CPU_STATE (cpu);
+ int length_read;
+
+ length_read = sim_core_read_buffer (sd, cpu, read_map, myaddr, memaddr,
+ length);
+ if (length_read != length)
+ return EIO;
+ return 0;
+}
+
+/* Memory error support for an opcodes disassembler. */
+
+void
+sim_disasm_perror_memory (int status, bfd_vma memaddr,
+ struct disassemble_info *info)
+{
+ if (status != EIO)
+ /* Can't happen. */
+ info->fprintf_func (info->stream, "Unknown error %d.", status);
+ else
+ /* Actually, address between memaddr and memaddr + len was
+ out of bounds. */
+ info->fprintf_func (info->stream,
+ "Address 0x%x is out of bounds.",
+ (int) memaddr);
+}
+
+/* Disassemble using the CGEN opcode table.
+ ??? While executing an instruction, the insn has been decoded and all its
+ fields have been extracted. It is certainly possible to do the disassembly
+ with that data. This seems simpler, but maybe in the future the already
+ extracted fields will be used. */
+
+void
+sim_cgen_disassemble_insn (SIM_CPU *cpu, const CGEN_INSN *insn,
+ const ARGBUF *abuf, IADDR pc, char *buf)
+{
+ unsigned int length;
+ unsigned long insn_value;
+ struct disassemble_info disasm_info;
+ SFILE sfile;
+ union {
+ unsigned8 bytes[CGEN_MAX_INSN_SIZE];
+ unsigned16 shorts[8];
+ unsigned32 words[4];
+ } insn_buf;
+ SIM_DESC sd = CPU_STATE (cpu);
+ CGEN_CPU_DESC cd = CPU_CPU_DESC (cpu);
+ CGEN_EXTRACT_INFO ex_info;
+ CGEN_FIELDS *fields = alloca (CGEN_CPU_SIZEOF_FIELDS (cd));
+ int insn_bit_length = CGEN_INSN_BITSIZE (insn);
+ int insn_length = insn_bit_length / 8;
+
+ sfile.buffer = sfile.current = buf;
+ INIT_DISASSEMBLE_INFO (disasm_info, (FILE *) &sfile,
+ (fprintf_ftype) sim_disasm_sprintf);
+ disasm_info.endian =
+ (bfd_big_endian (STATE_PROG_BFD (sd)) ? BFD_ENDIAN_BIG
+ : bfd_little_endian (STATE_PROG_BFD (sd)) ? BFD_ENDIAN_LITTLE
+ : BFD_ENDIAN_UNKNOWN);
+
+ length = sim_core_read_buffer (sd, cpu, read_map, &insn_buf, pc,
+ insn_length);
+
+ switch (min (cd->base_insn_bitsize, insn_bit_length))
+ {
+ case 0 : return; /* fake insn, typically "compile" (aka "invalid") */
+ case 8 : insn_value = insn_buf.bytes[0]; break;
+ case 16 : insn_value = T2H_2 (insn_buf.shorts[0]); break;
+ case 32 : insn_value = T2H_4 (insn_buf.words[0]); break;
+ default: abort ();
+ }
+
+ disasm_info.buffer_vma = pc;
+ disasm_info.buffer = insn_buf.bytes;
+ disasm_info.buffer_length = length;
+
+ ex_info.dis_info = (PTR) &disasm_info;
+ ex_info.valid = (1 << length) - 1;
+ ex_info.insn_bytes = insn_buf.bytes;
+
+ length = (*CGEN_EXTRACT_FN (cd, insn)) (cd, insn, &ex_info, insn_value, fields, pc);
+ /* Result of extract fn is in bits. */
+ /* ??? This assumes that each instruction has a fixed length (and thus
+ for insns with multiple versions of variable lengths they would each
+ have their own table entry). */
+ if (length == insn_bit_length)
+ {
+ (*CGEN_PRINT_FN (cd, insn)) (cd, &disasm_info, insn, fields, pc, length);
+ }
+ else
+ {
+ /* This shouldn't happen, but aborting is too drastic. */
+ strcpy (buf, "***unknown***");
+ }
+}
projects / deliverable / binutils-gdb.git / blobdiff