ARC: [mm] Assume pagecache page dirty by default

[deliverable/linux.git] / arch / arc / mm / tlb.c

diff --git a/arch/arc/mm/tlb.c b/arch/arc/mm/tlb.c
index fe1c5a073afe4cf996d28b6486c6b296fbd94344..d44ae33c2d1e61a4a432ee31ec2214a6668a8fc5 100644 (file)
--- a/arch/arc/mm/tlb.c
+++ b/arch/arc/mm/tlb.c
@@ -55,7 +55,7 @@
 #include <asm/arcregs.h>
 #include <asm/setup.h>
 #include <asm/mmu_context.h>
-#include <asm/tlb.h>
+#include <asm/mmu.h>
 
 /*                     Need for ARC MMU v2
  *
@@ -97,6 +97,7 @@
  * J-TLB entry got evicted/replaced.
  */
 
+
 /* A copy of the ASID from the PID reg is kept in asid_cache */
 int asid_cache = FIRST_ASID;
 
@@ -432,9 +433,14 @@ void update_mmu_cache(struct vm_area_struct *vma, unsigned long vaddr_unaligned,
 {
        unsigned long vaddr = vaddr_unaligned & PAGE_MASK;
        unsigned long paddr = pte_val(*ptep) & PAGE_MASK;
+       struct page *page = pfn_to_page(pte_pfn(*ptep));
 
        create_tlb(vma, vaddr, ptep);
 
+       if (page == ZERO_PAGE(0)) {
+               return;
+       }
+
        /*
         * Exec page : Independent of aliasing/page-color considerations,
         *             since icache doesn't snoop dcache on ARC, any dirty
@@ -446,9 +452,8 @@ void update_mmu_cache(struct vm_area_struct *vma, unsigned long vaddr_unaligned,
         */
        if ((vma->vm_flags & VM_EXEC) ||
             addr_not_cache_congruent(paddr, vaddr)) {
-               struct page *page = pfn_to_page(pte_pfn(*ptep));
 
-               int dirty = test_and_clear_bit(PG_arch_1, &page->flags);
+               int dirty = !test_and_set_bit(PG_dc_clean, &page->flags);
                if (dirty) {
                        /* wback + inv dcache lines */
                        __flush_dcache_page(paddr, paddr);
@@ -466,10 +471,25 @@ void update_mmu_cache(struct vm_area_struct *vma, unsigned long vaddr_unaligned,
  */
 void __cpuinit read_decode_mmu_bcr(void)
 {
-       unsigned int tmp;
-       struct bcr_mmu_1_2 *mmu2;       /* encoded MMU2 attr */
-       struct bcr_mmu_3 *mmu3;         /* encoded MMU3 attr */
        struct cpuinfo_arc_mmu *mmu = &cpuinfo_arc700[smp_processor_id()].mmu;
+       unsigned int tmp;
+       struct bcr_mmu_1_2 {
+#ifdef CONFIG_CPU_BIG_ENDIAN
+               unsigned int ver:8, ways:4, sets:4, u_itlb:8, u_dtlb:8;
+#else
+               unsigned int u_dtlb:8, u_itlb:8, sets:4, ways:4, ver:8;
+#endif
+       } *mmu2;
+
+       struct bcr_mmu_3 {
+#ifdef CONFIG_CPU_BIG_ENDIAN
+       unsigned int ver:8, ways:4, sets:4, osm:1, reserv:3, pg_sz:4,
+                    u_itlb:4, u_dtlb:4;
+#else
+       unsigned int u_dtlb:4, u_itlb:4, pg_sz:4, reserv:3, osm:1, sets:4,
+                    ways:4, ver:8;
+#endif
+       } *mmu3;
 
        tmp = read_aux_reg(ARC_REG_MMU_BCR);
        mmu->ver = (tmp >> 24);
@@ -505,7 +525,7 @@ char *arc_mmu_mumbojumbo(int cpu_id, char *buf, int len)
                       "J-TLB %d (%dx%d), uDTLB %d, uITLB %d, %s\n",
                       p_mmu->num_tlb, p_mmu->sets, p_mmu->ways,
                       p_mmu->u_dtlb, p_mmu->u_itlb,
-                      __CONFIG_ARC_MMU_SASID_VAL ? "SASID" : "");
+                      IS_ENABLED(CONFIG_ARC_MMU_SASID) ? "SASID" : "");
 
        return buf;
 }