ARM: pb1176: add ICST307 clocks to the device tree

[deliverable/linux.git] / arch / arm / boot / dts / arm-realview-pb1176.dts

diff --git a/arch/arm/boot/dts/arm-realview-pb1176.dts b/arch/arm/boot/dts/arm-realview-pb1176.dts
index 1bc64cda819e0b70530575ed1ec6d5c57e19b075..d0855bf736112f0f705393f5ba84de3e1baf4b2a 100644 (file)
--- a/arch/arm/boot/dts/arm-realview-pb1176.dts
+++ b/arch/arm/boot/dts/arm-realview-pb1176.dts
@@ -106,6 +106,31 @@
                clock-frequency = <0>;
        };
 
+       flash@30000000 {
+               compatible = "arm,versatile-flash", "cfi-flash";
+               reg = <0x30000000 0x4000000>;
+               bank-width = <4>;
+       };
+
+       fpga_flash@38000000 {
+               compatible = "arm,versatile-flash", "cfi-flash";
+               reg = <0x38000000 0x800000>;
+               bank-width = <4>;
+       };
+
+       /*
+        * The "secure flash" contains things like the boot
+        * monitor so we don't want people to accidentally
+        * screw this up. Mark the device tree node disabled
+        * by default.
+        */
+       secflash@3c000000 {
+               compatible = "arm,versatile-flash", "cfi-flash";
+               reg = <0x3c000000 0x4000000>;
+               bank-width = <4>;
+               status = "disabled";
+       };
+
        soc {
                #address-cells = <1>;
                #size-cells = <1>;
@@ -176,6 +201,41 @@
                                label = "versatile:7";
                                default-state = "off";
                        };
+                       oscclk0: osc0@0c {
+                               compatible = "arm,syscon-icst307";
+                               #clock-cells = <0>;
+                               lock-offset = <0x20>;
+                               vco-offset = <0x0C>;
+                               clocks = <&xtal24mhz>;
+                       };
+                       oscclk1: osc1@10 {
+                               compatible = "arm,syscon-icst307";
+                               #clock-cells = <0>;
+                               lock-offset = <0x20>;
+                               vco-offset = <0x10>;
+                               clocks = <&xtal24mhz>;
+                       };
+                       oscclk2: osc2@14 {
+                               compatible = "arm,syscon-icst307";
+                               #clock-cells = <0>;
+                               lock-offset = <0x20>;
+                               vco-offset = <0x14>;
+                               clocks = <&xtal24mhz>;
+                       };
+                       oscclk3: osc3@18 {
+                               compatible = "arm,syscon-icst307";
+                               #clock-cells = <0>;
+                               lock-offset = <0x20>;
+                               vco-offset = <0x18>;
+                               clocks = <&xtal24mhz>;
+                       };
+                       oscclk4: osc4@1c {
+                               compatible = "arm,syscon-icst307";
+                               #clock-cells = <0>;
+                               lock-offset = <0x20>;
+                               vco-offset = <0x1c>;
+                               clocks = <&xtal24mhz>;
+                       };
                };
 
                /* Primary DevChip GIC synthesized with the CPU */
@@ -297,6 +357,13 @@
                        clocks = <&uartclk>, <&pclk>;
                        clock-names = "uartclk", "apb_pclk";
                };
+
+               /* Direct-mapped development chip ROM */
+               pb1176_rom@10200000 {
+                       compatible = "direct-mapped";
+                       reg = <0x10200000 0x4000>;
+                       bank-width = <1>;
+               };
        };
 
        /* These peripherals are inside the FPGA rather than the DevChip */