Merge branch 'pm-cpufreq-fixes'

[deliverable/linux.git] / arch / arm / boot / dts / logicpd-torpedo-som.dtsi

diff --git a/arch/arm/boot/dts/logicpd-torpedo-som.dtsi b/arch/arm/boot/dts/logicpd-torpedo-som.dtsi
index 00805322367e7eb73bcc4ba5bda124eee5372467..5e9a13c0eaf7f4ca515942438cc1c8cdc331eafd 100644 (file)
--- a/arch/arm/boot/dts/logicpd-torpedo-som.dtsi
+++ b/arch/arm/boot/dts/logicpd-torpedo-som.dtsi
@@ -35,11 +35,15 @@
 };
 
 &gpmc {
-       ranges = <0 0 0x00000000 0x1000000>;    /* CS0: 16MB for NAND */
+       ranges = <0 0 0x30000000 0x1000000>;    /* CS0: 16MB for NAND */
 
        nand@0,0 {
-               linux,mtd-name = "micron,mt29f4g16abbda3w";
+               compatible = "ti,omap2-nand";
                reg = <0 0 4>; /* CS0, offset 0, IO size 4 */
+               interrupt-parent = <&gpmc>;
+               interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */
+                            <1 IRQ_TYPE_NONE>; /* termcount */
+               linux,mtd-name = "micron,mt29f4g16abbda3w";
                nand-bus-width = <16>;
                ti,nand-ecc-opt = "bch8";
                gpmc,sync-clk-ps = <0>;
@@ -110,6 +114,11 @@
 
 &i2c3 {
        clock-frequency = <400000>;
+       at24@50 {
+               compatible = "at24,24c02";
+               readonly;
+               reg = <0x50>;
+       };
 };
 
 /*
@@ -167,6 +176,31 @@
                        OMAP3_CORE1_IOPAD(0x2198, PIN_OUTPUT | MUX_MODE4)       /* GPIO_162,BT_EN */
                >;
        };
+       mcspi1_pins: pinmux_mcspi1_pins {
+               pinctrl-single,pins = <
+                       OMAP3_CORE1_IOPAD(0x21c8, PIN_INPUT | MUX_MODE0)        /* mcspi1_clk.mcspi1_clk */
+                       OMAP3_CORE1_IOPAD(0x21ca, PIN_OUTPUT | MUX_MODE0)       /* mcspi1_simo.mcspi1_simo */
+                       OMAP3_CORE1_IOPAD(0x21cc, PIN_INPUT_PULLUP | MUX_MODE0) /* mcspi1_somi.mcspi1_somi */
+                       OMAP3_CORE1_IOPAD(0x21ce, PIN_OUTPUT | MUX_MODE0)       /* mcspi1_cs0.mcspi1_cs0 */
+               >;
+       };
+       hsusb_otg_pins: pinmux_hsusb_otg_pins {
+               pinctrl-single,pins = <
+                       OMAP3_CORE1_IOPAD(0x21a2, PIN_INPUT | MUX_MODE0)        /* hsusb0_clk.hsusb0_clk */
+                       OMAP3_CORE1_IOPAD(0x21a4, PIN_OUTPUT | MUX_MODE0)       /* hsusb0_stp.hsusb0_stp */
+                       OMAP3_CORE1_IOPAD(0x21a6, PIN_INPUT | MUX_MODE0)        /* hsusb0_dir.hsusb0_dir */
+                       OMAP3_CORE1_IOPAD(0x21a8, PIN_INPUT | MUX_MODE0)        /* hsusb0_nxt.hsusb0_nxt */
+
+                       OMAP3_CORE1_IOPAD(0x21aa, PIN_INPUT | MUX_MODE0)        /* hsusb0_data0.hsusb0_data0 */
+                       OMAP3_CORE1_IOPAD(0x21ac, PIN_INPUT | MUX_MODE0)        /* hsusb0_data1.hsusb0_data1 */
+                       OMAP3_CORE1_IOPAD(0x21ae, PIN_INPUT | MUX_MODE0)        /* hsusb0_data2.hsusb0_data2 */
+                       OMAP3_CORE1_IOPAD(0x21b0, PIN_INPUT | MUX_MODE0)        /* hsusb0_data3.hsusb0_data3 */
+                       OMAP3_CORE1_IOPAD(0x21b2, PIN_INPUT | MUX_MODE0)        /* hsusb0_data4.hsusb0_data4 */
+                       OMAP3_CORE1_IOPAD(0x21b4, PIN_INPUT | MUX_MODE0)        /* hsusb0_data5.hsusb0_data5 */
+                       OMAP3_CORE1_IOPAD(0x21b6, PIN_INPUT | MUX_MODE0)        /* hsusb0_data6.hsusb0_data6 */
+                       OMAP3_CORE1_IOPAD(0x21b8, PIN_INPUT | MUX_MODE0)        /* hsusb0_data7.hsusb0_data7 */
+               >;
+       };
 };
 
 &uart2 {
@@ -175,6 +209,11 @@
        pinctrl-0 = <&uart2_pins>;
 };
 
+&mcspi1 {
+       pinctrl-names = "default";
+       pinctrl-0 = <&mcspi1_pins>;
+};
+
 &omap3_pmx_core2 {
        mmc3_core2_pins: pinmux_mmc3_core2_pins {
                pinctrl-single,pins = <