m68knommu: general interrupt controller for ColdFire 532x parts

[deliverable/linux.git] / arch / m68knommu / platform / coldfire / intc-simr.c

diff --git a/arch/m68knommu/platform/coldfire/intc-simr.c b/arch/m68knommu/platform/coldfire/intc-simr.c
index 3b614a3508fcc6f639475901bfbbba8c7d2a5e98..86fc2047d7acd99409d6ae337ef0a127bbf90850 100644 (file)
--- a/arch/m68knommu/platform/coldfire/intc-simr.c
+++ b/arch/m68knommu/platform/coldfire/intc-simr.c
@@ -20,20 +20,32 @@
 
 static void intc_irq_mask(unsigned int irq)
 {
-       if ((irq >= MCFINT_VECBASE) && (irq <= MCFINT_VECBASE + 63))
-               __raw_writeb(irq - MCFINT_VECBASE, MCF_IPSBAR + MCFICM_INTC0 + MCFINTC_SIMR);
+       if (irq >= MCFINT_VECBASE) {
+               if (irq < MCFINT_VECBASE + 64)
+                       __raw_writeb(irq - MCFINT_VECBASE, MCFINTC0_SIMR);
+               else if ((irq < MCFINT_VECBASE + 128) && MCFINTC1_SIMR)
+                       __raw_writeb(irq - MCFINT_VECBASE - 64, MCFINTC1_SIMR);
+       }
 }
 
 static void intc_irq_unmask(unsigned int irq)
 {
-       if ((irq >= MCFINT_VECBASE) && (irq <= MCFINT_VECBASE + 63))
-               __raw_writeb(irq - MCFINT_VECBASE, MCF_IPSBAR + MCFICM_INTC0 + MCFINTC_CIMR);
+       if (irq >= MCFINT_VECBASE) {
+               if (irq < MCFINT_VECBASE + 64)
+                       __raw_writeb(irq - MCFINT_VECBASE, MCFINTC0_CIMR);
+               else if ((irq < MCFINT_VECBASE + 128) && MCFINTC1_CIMR)
+                       __raw_writeb(irq - MCFINT_VECBASE - 64, MCFINTC1_CIMR);
+       }
 }
 
 static int intc_irq_set_type(unsigned int irq, unsigned int type)
 {
-       if ((irq >= MCFINT_VECBASE) && (irq <= MCFINT_VECBASE + 63))
-               __raw_writeb(5, MCF_IPSBAR + MCFICM_INTC0 + MCFINTC_ICR0 + irq - MCFINT_VECBASE);
+       if (irq >= MCFINT_VECBASE) {
+               if (irq < MCFINT_VECBASE + 64)
+                       __raw_writeb(5, MCFINTC0_ICR0 + irq - MCFINT_VECBASE);
+               else if ((irq < MCFINT_VECBASE) && MCFINTC1_ICR0)
+                       __raw_writeb(5, MCFINTC1_ICR0 + irq - MCFINT_VECBASE - 64);
+       }
        return 0;
 }