MIPS: Mark cascade and low level interrupts IRQF_NO_THREAD

[deliverable/linux.git] / arch / mips / bcm63xx / irq.c

diff --git a/arch/mips/bcm63xx/irq.c b/arch/mips/bcm63xx/irq.c
index 1691531aa34d405d166b946a8739637cf312ec7d..162e11b4ed755f7e227d4cfc485d40170716abdf 100644 (file)
--- a/arch/mips/bcm63xx/irq.c
+++ b/arch/mips/bcm63xx/irq.c
@@ -222,6 +222,7 @@ static struct irq_chip bcm63xx_external_irq_chip = {
 static struct irqaction cpu_ip2_cascade_action = {
        .handler        = no_action,
        .name           = "cascade_ip2",
+       .flags          = IRQF_NO_THREAD,
 };
 
 void __init arch_init_irq(void)
@@ -230,11 +231,11 @@ void __init arch_init_irq(void)
 
        mips_cpu_irq_init();
        for (i = IRQ_INTERNAL_BASE; i < NR_IRQS; ++i)
-               set_irq_chip_and_handler(i, &bcm63xx_internal_irq_chip,
+               irq_set_chip_and_handler(i, &bcm63xx_internal_irq_chip,
                                         handle_level_irq);
 
        for (i = IRQ_EXT_BASE; i < IRQ_EXT_BASE + 4; ++i)
-               set_irq_chip_and_handler(i, &bcm63xx_external_irq_chip,
+               irq_set_chip_and_handler(i, &bcm63xx_external_irq_chip,
                                         handle_edge_irq);
 
        setup_irq(IRQ_MIPS_BASE + 2, &cpu_ip2_cascade_action);