MIPS: Whitespace cleanup.

[deliverable/linux.git] / arch / mips / include / asm / mach-pnx833x / pnx833x.h

diff --git a/arch/mips/include/asm/mach-pnx833x/pnx833x.h b/arch/mips/include/asm/mach-pnx833x/pnx833x.h
index 100f52870e3ce2a670e4c4e318b2f212593afe41..e6fc3a9d594a52d456b1154645491f14ca4dafee 100644 (file)
--- a/arch/mips/include/asm/mach-pnx833x/pnx833x.h
+++ b/arch/mips/include/asm/mach-pnx833x/pnx833x.h
@@ -73,7 +73,7 @@
 
 
 #define PNX833X_RESET_CONTROL          PNX833X_REG(0x8004)
-#define PNX833X_RESET_CONTROL_2        PNX833X_REG(0x8014)
+#define PNX833X_RESET_CONTROL_2                PNX833X_REG(0x8014)
 
 #define PNX833X_PIC_REG(offs)          PNX833X_REG(0x01000 + (offs))
 #define PNX833X_PIC_INT_PRIORITY       PNX833X_PIC_REG(0x0)
@@ -82,10 +82,10 @@
 #define PNX833X_PIC_INT_SRC_INT_SRC_SHIFT      3
 #define PNX833X_PIC_INT_REG(irq)       PNX833X_PIC_REG(0x10 + 4*(irq))
 
-#define PNX833X_CLOCK_CPUCP_CTL        PNX833X_REG(0x9228)
+#define PNX833X_CLOCK_CPUCP_CTL PNX833X_REG(0x9228)
 #define PNX833X_CLOCK_CPUCP_CTL_EXIT_RESET     0x00000002ul    /* bit 1 */
 #define PNX833X_CLOCK_CPUCP_CTL_DIV_CLOCK_MASK 0x00000018ul    /* bits 4:3 */
-#define PNX833X_CLOCK_CPUCP_CTL_DIV_CLOCK_SHIFT        3
+#define PNX833X_CLOCK_CPUCP_CTL_DIV_CLOCK_SHIFT 3
 
 #define PNX8335_CLOCK_PLL_CPU_CTL              PNX833X_REG(0x9020)
 #define PNX8335_CLOCK_PLL_CPU_CTL_FREQ_MASK    0x1f
@@ -149,7 +149,7 @@
 #define PNX833X_MIU_SEL0_SPI_MODE_ENABLE_MASK  (1 << 14)
 #define PNX833X_MIU_SEL0_SPI_MODE_ENABLE_SHIFT 14
 
-#define PNX833X_MIU_SEL0_BURST_MODE_ENABLE_MASK        (1 << 7)
+#define PNX833X_MIU_SEL0_BURST_MODE_ENABLE_MASK (1 << 7)
 #define PNX833X_MIU_SEL0_BURST_MODE_ENABLE_SHIFT       7
 
 #define PNX833X_MIU_SEL0_BURST_PAGE_LEN_MASK   (0xF << 9)
@@ -160,10 +160,10 @@
 #define PNX833X_MIU_CONFIG_SPI_OPCODE_MASK     (0xFF << 3)
 #define PNX833X_MIU_CONFIG_SPI_OPCODE_SHIFT    3
 
-#define PNX833X_MIU_CONFIG_SPI_DATA_ENABLE_MASK        (1 << 2)
+#define PNX833X_MIU_CONFIG_SPI_DATA_ENABLE_MASK (1 << 2)
 #define PNX833X_MIU_CONFIG_SPI_DATA_ENABLE_SHIFT       2
 
-#define PNX833X_MIU_CONFIG_SPI_ADDR_ENABLE_MASK        (1 << 1)
+#define PNX833X_MIU_CONFIG_SPI_ADDR_ENABLE_MASK (1 << 1)
 #define PNX833X_MIU_CONFIG_SPI_ADDR_ENABLE_SHIFT       1
 
 #define PNX833X_MIU_CONFIG_SPI_SYNC_MASK       (1 << 0)