MIPS: uasm: Add CFCMSA/CTCMSA instructions

[deliverable/linux.git] / arch / mips / include / uapi / asm / inst.h

diff --git a/arch/mips/include/uapi/asm/inst.h b/arch/mips/include/uapi/asm/inst.h
index 8051f9aa13796f5e6f63a249883b362072c99217..2e624dd058ef1566cc1bfb9dc24de0d6a7759df2 100644 (file)
--- a/arch/mips/include/uapi/asm/inst.h
+++ b/arch/mips/include/uapi/asm/inst.h
@@ -103,7 +103,7 @@ enum rt_op {
        bltzal_op, bgezal_op, bltzall_op, bgezall_op,
        rt_op_0x14, rt_op_0x15, rt_op_0x16, rt_op_0x17,
        rt_op_0x18, rt_op_0x19, rt_op_0x1a, rt_op_0x1b,
-       bposge32_op, rt_op_0x1d, rt_op_0x1e, rt_op_0x1f
+       bposge32_op, rt_op_0x1d, rt_op_0x1e, synci_op
 };
 
 /*
@@ -237,6 +237,21 @@ enum bshfl_func {
        seh_op  = 0x18,
 };
 
+/*
+ * MSA minor opcodes.
+ */
+enum msa_func {
+       msa_elm_op = 0x19,
+};
+
+/*
+ * MSA ELM opcodes.
+ */
+enum msa_elm {
+       msa_ctc_op = 0x3e,
+       msa_cfc_op = 0x7e,
+};
+
 /*
  * func field for MSA MI10 format.
  */
@@ -264,7 +279,7 @@ enum mm_major_op {
        mm_pool32b_op, mm_pool16b_op, mm_lhu16_op, mm_andi16_op,
        mm_addiu32_op, mm_lhu32_op, mm_sh32_op, mm_lh32_op,
        mm_pool32i_op, mm_pool16c_op, mm_lwsp16_op, mm_pool16d_op,
-       mm_ori32_op, mm_pool32f_op, mm_reserved1_op, mm_reserved2_op,
+       mm_ori32_op, mm_pool32f_op, mm_pool32s_op, mm_reserved2_op,
        mm_pool32c_op, mm_lwgp16_op, mm_lw16_op, mm_pool16e_op,
        mm_xori32_op, mm_jals32_op, mm_addiupc_op, mm_reserved3_op,
        mm_reserved4_op, mm_pool16f_op, mm_sb16_op, mm_beqz16_op,
@@ -478,6 +493,13 @@ enum mm_32f_73_minor_op {
        mm_fcvts1_op = 0xed,
 };
 
+/*
+ * (microMIPS) POOL32S minor opcodes.
+ */
+enum mm_32s_minor_op {
+       mm_32s_elm_op = 0x16,
+};
+
 /*
  * (microMIPS) POOL16C minor opcodes.
  */
@@ -586,6 +608,36 @@ struct r_format {                  /* Register format */
        ;))))))
 };
 
+struct c0r_format {                    /* C0 register format */
+       __BITFIELD_FIELD(unsigned int opcode : 6,
+       __BITFIELD_FIELD(unsigned int rs : 5,
+       __BITFIELD_FIELD(unsigned int rt : 5,
+       __BITFIELD_FIELD(unsigned int rd : 5,
+       __BITFIELD_FIELD(unsigned int z: 8,
+       __BITFIELD_FIELD(unsigned int sel : 3,
+       ;))))))
+};
+
+struct mfmc0_format {                  /* MFMC0 register format */
+       __BITFIELD_FIELD(unsigned int opcode : 6,
+       __BITFIELD_FIELD(unsigned int rs : 5,
+       __BITFIELD_FIELD(unsigned int rt : 5,
+       __BITFIELD_FIELD(unsigned int rd : 5,
+       __BITFIELD_FIELD(unsigned int re : 5,
+       __BITFIELD_FIELD(unsigned int sc : 1,
+       __BITFIELD_FIELD(unsigned int : 2,
+       __BITFIELD_FIELD(unsigned int sel : 3,
+       ;))))))))
+};
+
+struct co_format {                     /* C0 CO format */
+       __BITFIELD_FIELD(unsigned int opcode : 6,
+       __BITFIELD_FIELD(unsigned int co : 1,
+       __BITFIELD_FIELD(unsigned int code : 19,
+       __BITFIELD_FIELD(unsigned int func : 6,
+       ;))))
+};
+
 struct p_format {              /* Performance counter format (R10000) */
        __BITFIELD_FIELD(unsigned int opcode : 6,
        __BITFIELD_FIELD(unsigned int rs : 5,
@@ -937,6 +989,9 @@ union mips_instruction {
        struct u_format u_format;
        struct c_format c_format;
        struct r_format r_format;
+       struct c0r_format c0r_format;
+       struct mfmc0_format mfmc0_format;
+       struct co_format co_format;
        struct p_format p_format;
        struct f_format f_format;
        struct ma_format ma_format;