/* Main header file for the bfd library -- portable access to object files.
Copyright 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
- 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010, 2011
- Free Software Foundation, Inc.
+ 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010, 2011,
+ 2012 Free Software Foundation, Inc.
Contributed by Cygnus Support.
#ifndef __BFD_H_SEEN__
#define __BFD_H_SEEN__
+/* PR 14072: Ensure that config.h is included first. */
+#if !defined PACKAGE && !defined PACKAGE_VERSION
+#error config.h must be included before this header
+#endif
+
#ifdef __cplusplus
extern "C" {
#endif
#include "ansidecl.h"
#include "symcat.h"
+#include <sys/stat.h>
+
#if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
#ifndef SABER
/* This hack is to avoid a problem with some strict ANSI C preprocessors.
problem for example when trying to use STRING_COMMA_LEN to build
the arguments to the strncmp() macro. Hence this alternative
definition of strncmp is provided here.
-
+
Note - these macros do NOT work if STR2 is not a constant string. */
#define CONST_STRNEQ(STR1,STR2) (strncmp ((STR1), (STR2), sizeof (STR2) - 1) == 0)
/* strcpy() can have a similar problem, but since we know we are
typedef struct bfd_section *sec_ptr;
-#define bfd_get_section_name(bfd, ptr) ((ptr)->name + 0)
-#define bfd_get_section_vma(bfd, ptr) ((ptr)->vma + 0)
-#define bfd_get_section_lma(bfd, ptr) ((ptr)->lma + 0)
-#define bfd_get_section_alignment(bfd, ptr) ((ptr)->alignment_power + 0)
+#define bfd_get_section_name(bfd, ptr) ((void) bfd, (ptr)->name)
+#define bfd_get_section_vma(bfd, ptr) ((void) bfd, (ptr)->vma)
+#define bfd_get_section_lma(bfd, ptr) ((void) bfd, (ptr)->lma)
+#define bfd_get_section_alignment(bfd, ptr) ((void) bfd, \
+ (ptr)->alignment_power)
#define bfd_section_name(bfd, ptr) ((ptr)->name)
#define bfd_section_size(bfd, ptr) ((ptr)->size)
#define bfd_get_section_size(ptr) ((ptr)->size)
#define bfd_section_vma(bfd, ptr) ((ptr)->vma)
#define bfd_section_lma(bfd, ptr) ((ptr)->lma)
#define bfd_section_alignment(bfd, ptr) ((ptr)->alignment_power)
-#define bfd_get_section_flags(bfd, ptr) ((ptr)->flags + 0)
-#define bfd_get_section_userdata(bfd, ptr) ((ptr)->userdata)
+#define bfd_get_section_flags(bfd, ptr) ((void) bfd, (ptr)->flags)
+#define bfd_get_section_userdata(bfd, ptr) ((void) bfd, (ptr)->userdata)
#define bfd_is_com_section(ptr) (((ptr)->flags & SEC_IS_COMMON) != 0)
? (sec)->rawsize : (sec)->size) / bfd_octets_per_byte (bfd))
/* Return TRUE if input section SEC has been discarded. */
-#define elf_discarded_section(sec) \
+#define discarded_section(sec) \
(!bfd_is_abs_section (sec) \
&& bfd_is_abs_section ((sec)->output_section) \
- && (sec)->sec_info_type != ELF_INFO_TYPE_MERGE \
- && (sec)->sec_info_type != ELF_INFO_TYPE_JUST_SYMS)
-
-/* Forward define. */
-struct stat;
+ && (sec)->sec_info_type != SEC_INFO_TYPE_MERGE \
+ && (sec)->sec_info_type != SEC_INFO_TYPE_JUST_SYMS)
\f
typedef enum bfd_print_symbol
{
bfd_uint64_t bfd_get_bits (const void *, int, bfd_boolean);
void bfd_put_bits (bfd_uint64_t, void *, int, bfd_boolean);
-extern bfd_boolean bfd_section_already_linked_table_init (void);
-extern void bfd_section_already_linked_table_free (void);
-\f
-/* Externally visible ECOFF routines. */
-
#if defined(__STDC__) || defined(ALMOST_STDC)
struct ecoff_debug_info;
struct ecoff_debug_swap;
struct bfd_symbol;
struct bfd_link_info;
struct bfd_link_hash_entry;
+struct bfd_section_already_linked;
struct bfd_elf_version_tree;
#endif
+
+extern bfd_boolean bfd_section_already_linked_table_init (void);
+extern void bfd_section_already_linked_table_free (void);
+extern bfd_boolean _bfd_handle_already_linked
+ (struct bfd_section *, struct bfd_section_already_linked *,
+ struct bfd_link_info *);
+\f
+/* Externally visible ECOFF routines. */
+
extern bfd_vma bfd_ecoff_get_gp_value
(bfd * abfd);
extern bfd_boolean bfd_ecoff_set_gp_value
(bfd *, struct bfd_link_info *);
extern bfd_boolean bfd_elf_get_bfd_needed_list
(bfd *, struct bfd_link_needed_list **);
+extern bfd_boolean bfd_elf_stack_segment_size (bfd *, struct bfd_link_info *,
+ const char *, bfd_vma);
extern bfd_boolean bfd_elf_size_dynamic_sections
(bfd *, const char *, const char *, const char *, const char *, const char *,
- const char * const *, struct bfd_link_info *, struct bfd_section **,
- struct bfd_elf_version_tree *);
+ const char * const *, struct bfd_link_info *, struct bfd_section **);
extern bfd_boolean bfd_elf_size_dynsym_hash_dynstr
(bfd *, struct bfd_link_info *);
extern void bfd_elf_set_dt_needed_name
the remote memory. */
extern bfd *bfd_elf_bfd_from_remote_memory
(bfd *templ, bfd_vma ehdr_vma, bfd_vma *loadbasep,
- int (*target_read_memory) (bfd_vma vma, bfd_byte *myaddr, int len));
-
-/* Return the arch_size field of an elf bfd, or -1 if not elf. */
-extern int bfd_get_arch_size
- (bfd *);
-
-/* Return TRUE if address "naturally" sign extends, or -1 if not elf. */
-extern int bfd_get_sign_extend_vma
- (bfd *);
+ int (*target_read_memory) (bfd_vma vma, bfd_byte *myaddr,
+ bfd_size_type len));
extern struct bfd_section *_bfd_elf_tls_setup
(bfd *, struct bfd_link_info *);
+extern struct bfd_section *
+_bfd_nearby_section (bfd *, struct bfd_section *, bfd_vma);
+
extern void _bfd_fix_excluded_sec_syms
(bfd *, struct bfd_link_info *);
void bfd_elf32_arm_set_target_relocs
(bfd *, struct bfd_link_info *, int, char *, int, int, bfd_arm_vfp11_fix,
- int, int, int, int);
+ int, int, int, int, int);
extern bfd_boolean bfd_elf32_arm_get_bfd_for_interworking
(bfd *, struct bfd_link_info *);
extern unsigned int _bfd_elf_ppc_at_tprel_transform
(unsigned int, unsigned int);
+extern void bfd_elf64_aarch64_init_maps
+ (bfd *);
+
+void bfd_elf64_aarch64_set_options
+ (bfd *, struct bfd_link_info *, int, int, int);
+
+/* ELF AArch64 mapping symbol support. */
+#define BFD_AARCH64_SPECIAL_SYM_TYPE_MAP (1 << 0)
+#define BFD_AARCH64_SPECIAL_SYM_TYPE_TAG (1 << 1)
+#define BFD_AARCH64_SPECIAL_SYM_TYPE_OTHER (1 << 2)
+#define BFD_AARCH64_SPECIAL_SYM_TYPE_ANY (~0)
+extern bfd_boolean bfd_is_aarch64_special_symbol_name
+ (const char * name, int type);
+
+/* AArch64 stub generation support. Called from the linker. */
+extern int elf64_aarch64_setup_section_lists
+ (bfd *, struct bfd_link_info *);
+extern void elf64_aarch64_next_input_section
+ (struct bfd_link_info *, struct bfd_section *);
+extern bfd_boolean elf64_aarch64_size_stubs
+ (bfd *, bfd *, struct bfd_link_info *, bfd_signed_vma,
+ struct bfd_section * (*) (const char *, struct bfd_section *),
+ void (*) (void));
+extern bfd_boolean elf64_aarch64_build_stubs
+ (struct bfd_link_info *);
+
/* TI COFF load page support. */
extern void bfd_ticoff_set_section_load_page
(struct bfd_section *, int);
file_ptr bfd_get_size (bfd *abfd);
void *bfd_mmap (bfd *abfd, void *addr, bfd_size_type len,
- int prot, int flags, file_ptr offset);
+ int prot, int flags, file_ptr offset,
+ void **map_addr, bfd_size_type *map_len);
/* Extracted from bfdwin.c. */
/* Extracted from section.c. */
/* Type of sec_info information. */
unsigned int sec_info_type:3;
-#define ELF_INFO_TYPE_NONE 0
-#define ELF_INFO_TYPE_STABS 1
-#define ELF_INFO_TYPE_MERGE 2
-#define ELF_INFO_TYPE_EH_FRAME 3
-#define ELF_INFO_TYPE_JUST_SYMS 4
+#define SEC_INFO_TYPE_NONE 0
+#define SEC_INFO_TYPE_STABS 1
+#define SEC_INFO_TYPE_MERGE 2
+#define SEC_INFO_TYPE_EH_FRAME 3
+#define SEC_INFO_TYPE_JUST_SYMS 4
/* Nonzero if this section uses RELA relocations, rather than REL. */
unsigned int use_rela_p:1;
} asection;
/* Relax table contains information about instructions which can
- be removed by relaxation -- replacing a long address with a
+ be removed by relaxation -- replacing a long address with a
short address. */
struct relax_table {
/* Address where bytes may be deleted. */
bfd_vma addr;
-
+
/* Number of bytes to be deleted. */
int size;
};
/* These sections are global, and are managed by BFD. The application
and target back end are not permitted to change the values in
- these sections. New code should use the section_ptr macros rather
- than referring directly to the const sections. The const sections
- may eventually vanish. */
+ these sections. */
+extern asection _bfd_std_section[4];
+
#define BFD_ABS_SECTION_NAME "*ABS*"
#define BFD_UND_SECTION_NAME "*UND*"
#define BFD_COM_SECTION_NAME "*COM*"
#define BFD_IND_SECTION_NAME "*IND*"
-/* The absolute section. */
-extern asection bfd_abs_section;
-#define bfd_abs_section_ptr ((asection *) &bfd_abs_section)
-#define bfd_is_abs_section(sec) ((sec) == bfd_abs_section_ptr)
-/* Pointer to the undefined section. */
-extern asection bfd_und_section;
-#define bfd_und_section_ptr ((asection *) &bfd_und_section)
-#define bfd_is_und_section(sec) ((sec) == bfd_und_section_ptr)
/* Pointer to the common section. */
-extern asection bfd_com_section;
-#define bfd_com_section_ptr ((asection *) &bfd_com_section)
+#define bfd_com_section_ptr (&_bfd_std_section[0])
+/* Pointer to the undefined section. */
+#define bfd_und_section_ptr (&_bfd_std_section[1])
+/* Pointer to the absolute section. */
+#define bfd_abs_section_ptr (&_bfd_std_section[2])
/* Pointer to the indirect section. */
-extern asection bfd_ind_section;
-#define bfd_ind_section_ptr ((asection *) &bfd_ind_section)
+#define bfd_ind_section_ptr (&_bfd_std_section[3])
+
+#define bfd_is_und_section(sec) ((sec) == bfd_und_section_ptr)
+#define bfd_is_abs_section(sec) ((sec) == bfd_abs_section_ptr)
#define bfd_is_ind_section(sec) ((sec) == bfd_ind_section_ptr)
#define bfd_is_const_section(SEC) \
/* vma, lma, size, rawsize, compressed_size, relax, relax_count, */ \
0, 0, 0, 0, 0, 0, 0, \
\
- /* output_offset, output_section, alignment_power, */ \
- 0, (struct bfd_section *) &SEC, 0, \
+ /* output_offset, output_section, alignment_power, */ \
+ 0, &SEC, 0, \
\
/* relocation, orelocation, reloc_count, filepos, rel_filepos, */ \
NULL, NULL, 0, 0, 0, \
asection *bfd_get_section_by_name (bfd *abfd, const char *name);
+asection *bfd_get_next_section_by_name (asection *sec);
+
+asection *bfd_get_linker_section (bfd *abfd, const char *name);
+
asection *bfd_get_section_by_name_if
(bfd *abfd,
const char *name,
#define bfd_mach_sparc_64bit_p(mach) \
((mach) >= bfd_mach_sparc_v9 && (mach) != bfd_mach_sparc_v8plusb)
bfd_arch_spu, /* PowerPC SPU */
-#define bfd_mach_spu 256
+#define bfd_mach_spu 256
bfd_arch_mips, /* MIPS Rxxxx */
#define bfd_mach_mips3000 3000
#define bfd_mach_mips3900 3900
#define bfd_mach_mips5000 5000
#define bfd_mach_mips5400 5400
#define bfd_mach_mips5500 5500
+#define bfd_mach_mips5900 5900
#define bfd_mach_mips6000 6000
#define bfd_mach_mips7000 7000
#define bfd_mach_mips8000 8000
#define bfd_mach_mips_loongson_3a 3003
#define bfd_mach_mips_sb1 12310201 /* octal 'SB', 01 */
#define bfd_mach_mips_octeon 6501
+#define bfd_mach_mips_octeonp 6601
+#define bfd_mach_mips_octeon2 6502
#define bfd_mach_mips_xlr 887682 /* decimal 'XLR' */
#define bfd_mach_mipsisa32 32
#define bfd_mach_mipsisa32r2 33
#define bfd_mach_mipsisa64 64
#define bfd_mach_mipsisa64r2 65
+#define bfd_mach_mips_micromips 96
bfd_arch_i386, /* Intel 386 */
-#define bfd_mach_i386_i386 1
-#define bfd_mach_i386_i8086 2
-#define bfd_mach_i386_i386_intel_syntax 3
-#define bfd_mach_x64_32 32
-#define bfd_mach_x64_32_intel_syntax 33
-#define bfd_mach_x86_64 64
-#define bfd_mach_x86_64_intel_syntax 65
+#define bfd_mach_i386_intel_syntax (1 << 0)
+#define bfd_mach_i386_i8086 (1 << 1)
+#define bfd_mach_i386_i386 (1 << 2)
+#define bfd_mach_x86_64 (1 << 3)
+#define bfd_mach_x64_32 (1 << 4)
+#define bfd_mach_i386_i386_intel_syntax (bfd_mach_i386_i386 | bfd_mach_i386_intel_syntax)
+#define bfd_mach_x86_64_intel_syntax (bfd_mach_x86_64 | bfd_mach_i386_intel_syntax)
+#define bfd_mach_x64_32_intel_syntax (bfd_mach_x64_32 | bfd_mach_i386_intel_syntax)
bfd_arch_l1om, /* Intel L1OM */
-#define bfd_mach_l1om 66
-#define bfd_mach_l1om_intel_syntax 67
+#define bfd_mach_l1om (1 << 5)
+#define bfd_mach_l1om_intel_syntax (bfd_mach_l1om | bfd_mach_i386_intel_syntax)
+ bfd_arch_k1om, /* Intel K1OM */
+#define bfd_mach_k1om (1 << 6)
+#define bfd_mach_k1om_intel_syntax (bfd_mach_k1om | bfd_mach_i386_intel_syntax)
bfd_arch_we32k, /* AT&T WE32xxx */
bfd_arch_tahoe, /* CCI/Harris Tahoe */
bfd_arch_i860, /* Intel 860 */
#define bfd_mach_ppc_e500 500
#define bfd_mach_ppc_e500mc 5001
#define bfd_mach_ppc_e500mc64 5005
+#define bfd_mach_ppc_e5500 5006
+#define bfd_mach_ppc_e6500 5007
#define bfd_mach_ppc_titan 83
+#define bfd_mach_ppc_vle 84
bfd_arch_rs6000, /* IBM RS/6000 */
#define bfd_mach_rs6k 6000
#define bfd_mach_rs6k_rs1 6001
#define bfd_mach_m6812_default 0
#define bfd_mach_m6812 1
#define bfd_mach_m6812s 2
+ bfd_arch_m9s12x, /* Freescale S12X */
+ bfd_arch_m9s12xg, /* Freescale XGATE */
bfd_arch_z8k, /* Zilog Z8000 */
#define bfd_mach_z8001 1
#define bfd_mach_z8002 2
bfd_arch_tic6x, /* Texas Instruments TMS320C6X */
bfd_arch_tic80, /* TI TMS320c80 (MVP) */
bfd_arch_v850, /* NEC V850 */
+ bfd_arch_v850_rh850,/* NEC V850 (using RH850 ABI) */
#define bfd_mach_v850 1
#define bfd_mach_v850e 'E'
#define bfd_mach_v850e1 '1'
#define bfd_mach_v850e2 0x4532
#define bfd_mach_v850e2v3 0x45325633
+#define bfd_mach_v850e3v5 0x45335635 /* ('E'|'3'|'V'|'5') */
bfd_arch_arc, /* ARC Cores */
#define bfd_mach_arc_5 5
#define bfd_mach_arc_6 6
#define bfd_mach_mep 1
#define bfd_mach_mep_h1 0x6831
#define bfd_mach_mep_c5 0x6335
+ bfd_arch_metag,
+#define bfd_mach_metag 1
bfd_arch_ia64, /* HP/Intel ia64 */
#define bfd_mach_ia64_elf64 64
#define bfd_mach_ia64_elf32 32
bfd_arch_iq2000, /* Vitesse IQ2000. */
#define bfd_mach_iq2000 1
#define bfd_mach_iq10 2
+ bfd_arch_epiphany, /* Adapteva EPIPHANY */
+#define bfd_mach_epiphany16 1
+#define bfd_mach_epiphany32 2
bfd_arch_mt,
#define bfd_mach_ms1 1
#define bfd_mach_mrisc2 2
#define bfd_mach_cris_v0_v10 255
#define bfd_mach_cris_v32 32
#define bfd_mach_cris_v10_v32 1032
+ bfd_arch_rl78,
+#define bfd_mach_rl78 0x75
bfd_arch_rx, /* Renesas RX. */
#define bfd_mach_rx 0x75
bfd_arch_s390, /* IBM s390 */
#define bfd_mach_s390_31 31
#define bfd_mach_s390_64 64
- bfd_arch_score, /* Sunplus score */
+ bfd_arch_score, /* Sunplus score */
#define bfd_mach_score3 3
#define bfd_mach_score7 7
bfd_arch_openrisc, /* OpenRISC */
bfd_arch_xc16x, /* Infineon's XC16X Series. */
#define bfd_mach_xc16x 1
#define bfd_mach_xc16xl 2
-#define bfd_mach_xc16xs 3
+#define bfd_mach_xc16xs 3
+ bfd_arch_xgate, /* Freescale XGATE */
+#define bfd_mach_xgate 1
bfd_arch_xtensa, /* Tensilica's Xtensa cores. */
#define bfd_mach_xtensa 1
bfd_arch_z80,
bfd_arch_tilegx, /* Tilera TILE-Gx */
#define bfd_mach_tilepro 1
#define bfd_mach_tilegx 1
+#define bfd_mach_tilegx32 2
+ bfd_arch_aarch64, /* AArch64 */
+#define bfd_mach_aarch64 0
bfd_arch_last
};
bfd_boolean (*scan) (const struct bfd_arch_info *, const char *);
+ /* Allocate via bfd_malloc and return a fill buffer of size COUNT. If
+ IS_BIGENDIAN is TRUE, the order of bytes is big endian. If CODE is
+ TRUE, the buffer contains code. */
+ void *(*fill) (bfd_size_type count, bfd_boolean is_bigendian,
+ bfd_boolean code);
+
const struct bfd_arch_info *next;
}
bfd_arch_info_type;
BFD_RELOC_HI16_S_PLTOFF,
BFD_RELOC_8_PLTOFF,
+/* Size relocations. */
+ BFD_RELOC_SIZE32,
+ BFD_RELOC_SIZE64,
+
/* Relocations used by 68K ELF. */
BFD_RELOC_68K_GLOB_DAT,
BFD_RELOC_68K_JMP_SLOT,
BFD_RELOC_SPARC_M44,
BFD_RELOC_SPARC_L44,
BFD_RELOC_SPARC_REGISTER,
+ BFD_RELOC_SPARC_H34,
+ BFD_RELOC_SPARC_SIZE32,
+ BFD_RELOC_SPARC_SIZE64,
+ BFD_RELOC_SPARC_WDISP10,
/* SPARC little endian relocation */
BFD_RELOC_SPARC_REV32,
BFD_RELOC_ALPHA_TPREL_LO16,
BFD_RELOC_ALPHA_TPREL16,
-/* Bits 27..2 of the relocation address shifted right 2 bits;
-simple reloc otherwise. */
+/* The MIPS jump instruction. */
BFD_RELOC_MIPS_JMP,
+ BFD_RELOC_MICROMIPS_JMP,
/* The MIPS16 jump instruction. */
BFD_RELOC_MIPS16_JMP,
/* MIPS16 low 16 bits. */
BFD_RELOC_MIPS16_LO16,
+/* MIPS16 TLS relocations */
+ BFD_RELOC_MIPS16_TLS_GD,
+ BFD_RELOC_MIPS16_TLS_LDM,
+ BFD_RELOC_MIPS16_TLS_DTPREL_HI16,
+ BFD_RELOC_MIPS16_TLS_DTPREL_LO16,
+ BFD_RELOC_MIPS16_TLS_GOTTPREL,
+ BFD_RELOC_MIPS16_TLS_TPREL_HI16,
+ BFD_RELOC_MIPS16_TLS_TPREL_LO16,
+
/* Relocation against a MIPS literal section. */
BFD_RELOC_MIPS_LITERAL,
+ BFD_RELOC_MICROMIPS_LITERAL,
+
+/* microMIPS PC-relative relocations. */
+ BFD_RELOC_MICROMIPS_7_PCREL_S1,
+ BFD_RELOC_MICROMIPS_10_PCREL_S1,
+ BFD_RELOC_MICROMIPS_16_PCREL_S1,
+
+/* microMIPS versions of generic BFD relocs. */
+ BFD_RELOC_MICROMIPS_GPREL16,
+ BFD_RELOC_MICROMIPS_HI16,
+ BFD_RELOC_MICROMIPS_HI16_S,
+ BFD_RELOC_MICROMIPS_LO16,
/* MIPS ELF relocations. */
BFD_RELOC_MIPS_GOT16,
+ BFD_RELOC_MICROMIPS_GOT16,
BFD_RELOC_MIPS_CALL16,
+ BFD_RELOC_MICROMIPS_CALL16,
BFD_RELOC_MIPS_GOT_HI16,
+ BFD_RELOC_MICROMIPS_GOT_HI16,
BFD_RELOC_MIPS_GOT_LO16,
+ BFD_RELOC_MICROMIPS_GOT_LO16,
BFD_RELOC_MIPS_CALL_HI16,
+ BFD_RELOC_MICROMIPS_CALL_HI16,
BFD_RELOC_MIPS_CALL_LO16,
+ BFD_RELOC_MICROMIPS_CALL_LO16,
BFD_RELOC_MIPS_SUB,
+ BFD_RELOC_MICROMIPS_SUB,
BFD_RELOC_MIPS_GOT_PAGE,
+ BFD_RELOC_MICROMIPS_GOT_PAGE,
BFD_RELOC_MIPS_GOT_OFST,
+ BFD_RELOC_MICROMIPS_GOT_OFST,
BFD_RELOC_MIPS_GOT_DISP,
+ BFD_RELOC_MICROMIPS_GOT_DISP,
BFD_RELOC_MIPS_SHIFT5,
BFD_RELOC_MIPS_SHIFT6,
BFD_RELOC_MIPS_INSERT_A,
BFD_RELOC_MIPS_INSERT_B,
BFD_RELOC_MIPS_DELETE,
BFD_RELOC_MIPS_HIGHEST,
+ BFD_RELOC_MICROMIPS_HIGHEST,
BFD_RELOC_MIPS_HIGHER,
+ BFD_RELOC_MICROMIPS_HIGHER,
BFD_RELOC_MIPS_SCN_DISP,
+ BFD_RELOC_MICROMIPS_SCN_DISP,
BFD_RELOC_MIPS_REL16,
BFD_RELOC_MIPS_RELGOT,
BFD_RELOC_MIPS_JALR,
+ BFD_RELOC_MICROMIPS_JALR,
BFD_RELOC_MIPS_TLS_DTPMOD32,
BFD_RELOC_MIPS_TLS_DTPREL32,
BFD_RELOC_MIPS_TLS_DTPMOD64,
BFD_RELOC_MIPS_TLS_DTPREL64,
BFD_RELOC_MIPS_TLS_GD,
+ BFD_RELOC_MICROMIPS_TLS_GD,
BFD_RELOC_MIPS_TLS_LDM,
+ BFD_RELOC_MICROMIPS_TLS_LDM,
BFD_RELOC_MIPS_TLS_DTPREL_HI16,
+ BFD_RELOC_MICROMIPS_TLS_DTPREL_HI16,
BFD_RELOC_MIPS_TLS_DTPREL_LO16,
+ BFD_RELOC_MICROMIPS_TLS_DTPREL_LO16,
BFD_RELOC_MIPS_TLS_GOTTPREL,
+ BFD_RELOC_MICROMIPS_TLS_GOTTPREL,
BFD_RELOC_MIPS_TLS_TPREL32,
BFD_RELOC_MIPS_TLS_TPREL64,
BFD_RELOC_MIPS_TLS_TPREL_HI16,
+ BFD_RELOC_MICROMIPS_TLS_TPREL_HI16,
BFD_RELOC_MIPS_TLS_TPREL_LO16,
+ BFD_RELOC_MICROMIPS_TLS_TPREL_LO16,
/* MIPS ELF relocations (VxWorks and PLT extensions). */
relaxation. */
BFD_RELOC_MN10300_ALIGN,
+/* Various TLS-related relocations. */
+ BFD_RELOC_MN10300_TLS_GD,
+ BFD_RELOC_MN10300_TLS_LD,
+ BFD_RELOC_MN10300_TLS_LDO,
+ BFD_RELOC_MN10300_TLS_GOTIE,
+ BFD_RELOC_MN10300_TLS_IE,
+ BFD_RELOC_MN10300_TLS_LE,
+ BFD_RELOC_MN10300_TLS_DTPMOD,
+ BFD_RELOC_MN10300_TLS_DTPOFF,
+ BFD_RELOC_MN10300_TLS_TPOFF,
+
+/* This is a 32bit pcrel reloc for the mn10300, offset by two bytes in the
+instruction. */
+ BFD_RELOC_MN10300_32_PCREL,
+
+/* This is a 16bit pcrel reloc for the mn10300, offset by two bytes in the
+instruction. */
+ BFD_RELOC_MN10300_16_PCREL,
+
/* i386/elf relocations */
BFD_RELOC_386_GOT32,
BFD_RELOC_PPC_EMB_RELST_HA,
BFD_RELOC_PPC_EMB_BIT_FLD,
BFD_RELOC_PPC_EMB_RELSDA,
+ BFD_RELOC_PPC_VLE_REL8,
+ BFD_RELOC_PPC_VLE_REL15,
+ BFD_RELOC_PPC_VLE_REL24,
+ BFD_RELOC_PPC_VLE_LO16A,
+ BFD_RELOC_PPC_VLE_LO16D,
+ BFD_RELOC_PPC_VLE_HI16A,
+ BFD_RELOC_PPC_VLE_HI16D,
+ BFD_RELOC_PPC_VLE_HA16A,
+ BFD_RELOC_PPC_VLE_HA16D,
+ BFD_RELOC_PPC_VLE_SDA21,
+ BFD_RELOC_PPC_VLE_SDA21_LO,
+ BFD_RELOC_PPC_VLE_SDAREL_LO16A,
+ BFD_RELOC_PPC_VLE_SDAREL_LO16D,
+ BFD_RELOC_PPC_VLE_SDAREL_HI16A,
+ BFD_RELOC_PPC_VLE_SDAREL_HI16D,
+ BFD_RELOC_PPC_VLE_SDAREL_HA16A,
+ BFD_RELOC_PPC_VLE_SDAREL_HA16D,
BFD_RELOC_PPC64_HIGHER,
BFD_RELOC_PPC64_HIGHER_S,
BFD_RELOC_PPC64_HIGHEST,
/* start data in text. */
BFD_RELOC_V850_DATA,
-/* This is a 32bit pcrel reloc for the mn10300, offset by two bytes in the
-instruction. */
- BFD_RELOC_MN10300_32_PCREL,
-
-/* This is a 16bit pcrel reloc for the mn10300, offset by two bytes in the
-instruction. */
- BFD_RELOC_MN10300_16_PCREL,
-
/* This is a 8bit DP reloc for the tms320c30, where the most
significant 8 bits of a 24 bit word are placed into the least
significant 8 bits of the opcode. */
BFD_RELOC_MEP_GNU_VTENTRY,
+/* Imagination Technologies Meta relocations. */
+ BFD_RELOC_METAG_HIADDR16,
+ BFD_RELOC_METAG_LOADDR16,
+ BFD_RELOC_METAG_RELBRANCH,
+ BFD_RELOC_METAG_GETSETOFF,
+ BFD_RELOC_METAG_HIOG,
+ BFD_RELOC_METAG_LOOG,
+ BFD_RELOC_METAG_REL8,
+ BFD_RELOC_METAG_REL16,
+ BFD_RELOC_METAG_HI16_GOTOFF,
+ BFD_RELOC_METAG_LO16_GOTOFF,
+ BFD_RELOC_METAG_GETSET_GOTOFF,
+ BFD_RELOC_METAG_GETSET_GOT,
+ BFD_RELOC_METAG_HI16_GOTPC,
+ BFD_RELOC_METAG_LO16_GOTPC,
+ BFD_RELOC_METAG_HI16_PLT,
+ BFD_RELOC_METAG_LO16_PLT,
+ BFD_RELOC_METAG_RELBRANCH_PLT,
+ BFD_RELOC_METAG_GOTOFF,
+ BFD_RELOC_METAG_PLT,
+ BFD_RELOC_METAG_COPY,
+ BFD_RELOC_METAG_JMP_SLOT,
+ BFD_RELOC_METAG_RELATIVE,
+ BFD_RELOC_METAG_GLOB_DAT,
+ BFD_RELOC_METAG_TLS_GD,
+ BFD_RELOC_METAG_TLS_LDM,
+ BFD_RELOC_METAG_TLS_LDO_HI16,
+ BFD_RELOC_METAG_TLS_LDO_LO16,
+ BFD_RELOC_METAG_TLS_LDO,
+ BFD_RELOC_METAG_TLS_IE,
+ BFD_RELOC_METAG_TLS_IENONPIC,
+ BFD_RELOC_METAG_TLS_IENONPIC_HI16,
+ BFD_RELOC_METAG_TLS_IENONPIC_LO16,
+ BFD_RELOC_METAG_TLS_TPOFF,
+ BFD_RELOC_METAG_TLS_DTPMOD,
+ BFD_RELOC_METAG_TLS_DTPOFF,
+ BFD_RELOC_METAG_TLS_LE,
+ BFD_RELOC_METAG_TLS_LE_HI16,
+ BFD_RELOC_METAG_TLS_LE_LO16,
+
/* These are relocations for the GETA instruction. */
BFD_RELOC_MMIX_GETA,
BFD_RELOC_MMIX_GETA_1,
command address) into 8 bit immediate value of LDI insn. */
BFD_RELOC_AVR_LO8_LDI_PM,
-/* This is a 16 bit reloc for the AVR that stores 8 bit value
+/* This is a 16 bit reloc for the AVR that stores 8 bit value
(command address) into 8 bit immediate value of LDI insn. If the address
is beyond the 128k boundary, the linker inserts a jump stub for this reloc
in the lower 128k. */
instructions */
BFD_RELOC_AVR_6_ADIW,
+/* This is a 8 bit reloc for the AVR that stores bits 0..7 of a symbol
+in .byte lo8(symbol) */
+ BFD_RELOC_AVR_8_LO,
+
+/* This is a 8 bit reloc for the AVR that stores bits 8..15 of a symbol
+in .byte hi8(symbol) */
+ BFD_RELOC_AVR_8_HI,
+
+/* This is a 8 bit reloc for the AVR that stores bits 16..23 of a symbol
+in .byte hlo8(symbol) */
+ BFD_RELOC_AVR_8_HLO,
+
+/* Renesas RL78 Relocations. */
+ BFD_RELOC_RL78_NEG8,
+ BFD_RELOC_RL78_NEG16,
+ BFD_RELOC_RL78_NEG24,
+ BFD_RELOC_RL78_NEG32,
+ BFD_RELOC_RL78_16_OP,
+ BFD_RELOC_RL78_24_OP,
+ BFD_RELOC_RL78_32_OP,
+ BFD_RELOC_RL78_8U,
+ BFD_RELOC_RL78_16U,
+ BFD_RELOC_RL78_24U,
+ BFD_RELOC_RL78_DIR3U_PCREL,
+ BFD_RELOC_RL78_DIFF,
+ BFD_RELOC_RL78_GPRELB,
+ BFD_RELOC_RL78_GPRELW,
+ BFD_RELOC_RL78_GPRELL,
+ BFD_RELOC_RL78_SYM,
+ BFD_RELOC_RL78_OP_SUBTRACT,
+ BFD_RELOC_RL78_OP_NEG,
+ BFD_RELOC_RL78_OP_AND,
+ BFD_RELOC_RL78_OP_SHRA,
+ BFD_RELOC_RL78_ABS8,
+ BFD_RELOC_RL78_ABS16,
+ BFD_RELOC_RL78_ABS16_REV,
+ BFD_RELOC_RL78_ABS32,
+ BFD_RELOC_RL78_ABS32_REV,
+ BFD_RELOC_RL78_ABS16U,
+ BFD_RELOC_RL78_ABS16UW,
+ BFD_RELOC_RL78_ABS16UL,
+ BFD_RELOC_RL78_RELAX,
+ BFD_RELOC_RL78_HI16,
+ BFD_RELOC_RL78_HI8,
+ BFD_RELOC_RL78_LO16,
+
/* Renesas RX Relocations. */
BFD_RELOC_RX_NEG8,
BFD_RELOC_RX_NEG16,
BFD_RELOC_390_GOTPLT20,
BFD_RELOC_390_TLS_GOTIE20,
+/* STT_GNU_IFUNC relocation. */
+ BFD_RELOC_390_IRELATIVE,
+
/* Score relocations
Low 16 bit for load/store */
BFD_RELOC_SCORE_GPREL15,
This is the 5 bits of a value. */
BFD_RELOC_M68HC12_5B,
+/* Freescale XGATE reloc.
+This reloc marks the beginning of a bra/jal instruction. */
+ BFD_RELOC_XGATE_RL_JUMP,
+
+/* Freescale XGATE reloc.
+This reloc marks a group of several instructions that gcc generates
+and for which the linker relaxation pass can modify and/or remove
+some of them. */
+ BFD_RELOC_XGATE_RL_GROUP,
+
+/* Freescale XGATE reloc.
+This is the 16-bit lower part of an address. It is used for the '16-bit'
+instructions. */
+ BFD_RELOC_XGATE_LO16,
+
+/* Freescale XGATE reloc. */
+ BFD_RELOC_XGATE_GPAGE,
+
+/* Freescale XGATE reloc. */
+ BFD_RELOC_XGATE_24,
+
+/* Freescale XGATE reloc.
+This is a 9-bit pc-relative reloc. */
+ BFD_RELOC_XGATE_PCREL_9,
+
+/* Freescale XGATE reloc.
+This is a 10-bit pc-relative reloc. */
+ BFD_RELOC_XGATE_PCREL_10,
+
+/* Freescale XGATE reloc.
+This is the 16-bit lower part of an address. It is used for the '16-bit'
+instructions. */
+ BFD_RELOC_XGATE_IMM8_LO,
+
+/* Freescale XGATE reloc.
+This is the 16-bit higher part of an address. It is used for the '16-bit'
+instructions. */
+ BFD_RELOC_XGATE_IMM8_HI,
+
+/* Freescale XGATE reloc.
+This is a 3-bit pc-relative reloc. */
+ BFD_RELOC_XGATE_IMM3,
+
+/* Freescale XGATE reloc.
+This is a 4-bit pc-relative reloc. */
+ BFD_RELOC_XGATE_IMM4,
+
+/* Freescale XGATE reloc.
+This is a 5-bit pc-relative reloc. */
+ BFD_RELOC_XGATE_IMM5,
+
+/* Motorola 68HC12 reloc.
+This is the 9 bits of a value. */
+ BFD_RELOC_M68HC12_9B,
+
+/* Motorola 68HC12 reloc.
+This is the 16 bits of a value. */
+ BFD_RELOC_M68HC12_16B,
+
+/* Motorola 68HC12/XGATE reloc.
+This is a PCREL9 branch. */
+ BFD_RELOC_M68HC12_9_PCREL,
+
+/* Motorola 68HC12/XGATE reloc.
+This is a PCREL10 branch. */
+ BFD_RELOC_M68HC12_10_PCREL,
+
+/* Motorola 68HC12/XGATE reloc.
+This is the 8 bit low part of an absolute address and immediately precedes
+a matching HI8XG part. */
+ BFD_RELOC_M68HC12_LO8XG,
+
+/* Motorola 68HC12/XGATE reloc.
+This is the 8 bit high part of an absolute address and immediately follows
+a matching LO8XG part. */
+ BFD_RELOC_M68HC12_HI8XG,
+
/* NS CR16C Relocations. */
BFD_RELOC_16C_NUM08,
BFD_RELOC_16C_NUM08_C,
BFD_RELOC_MACH_O_PAIR. */
BFD_RELOC_MACH_O_SECTDIFF,
+/* Like BFD_RELOC_MACH_O_SECTDIFF but with a local symbol. */
+ BFD_RELOC_MACH_O_LOCAL_SECTDIFF,
+
/* Pair of relocation. Contains the first symbol. */
BFD_RELOC_MACH_O_PAIR,
/* Same as BFD_RELOC_32_PCREL but with an implicit -4 addend. */
BFD_RELOC_MACH_O_X86_64_PCREL32_4,
-/* This is a 32 bit reloc for the microblaze that stores the
+/* This is a 32 bit reloc for the microblaze that stores the
low 16 bits of a value */
BFD_RELOC_MICROBLAZE_32_LO,
-/* This is a 32 bit pc-relative reloc for the microblaze that
+/* This is a 32 bit pc-relative reloc for the microblaze that
stores the low 16 bits of a value */
BFD_RELOC_MICROBLAZE_32_LO_PCREL,
-/* This is a 32 bit reloc for the microblaze that stores a
+/* This is a 32 bit reloc for the microblaze that stores a
value relative to the read-only small data area anchor */
BFD_RELOC_MICROBLAZE_32_ROSDA,
-/* This is a 32 bit reloc for the microblaze that stores a
+/* This is a 32 bit reloc for the microblaze that stores a
value relative to the read-write small data area anchor */
BFD_RELOC_MICROBLAZE_32_RWSDA,
-/* This is a 32 bit reloc for the microblaze to handle
+/* This is a 32 bit reloc for the microblaze to handle
expressions of the form "Symbol Op Symbol" */
BFD_RELOC_MICROBLAZE_32_SYM_OP_SYM,
-/* This is a 64 bit reloc that stores the 32 bit pc relative
-value in two words (with an imm instruction). No relocation is
+/* This is a 64 bit reloc that stores the 32 bit pc relative
+value in two words (with an imm instruction). No relocation is
done here - only used for relaxing */
BFD_RELOC_MICROBLAZE_64_NONE,
-/* This is a 64 bit reloc that stores the 32 bit pc relative
+/* This is a 64 bit reloc that stores the 32 bit pc relative
value in two words (with an imm instruction). The relocation is
PC-relative GOT offset */
BFD_RELOC_MICROBLAZE_64_GOTPC,
-/* This is a 64 bit reloc that stores the 32 bit pc relative
+/* This is a 64 bit reloc that stores the 32 bit pc relative
value in two words (with an imm instruction). The relocation is
GOT offset */
BFD_RELOC_MICROBLAZE_64_GOT,
-/* This is a 64 bit reloc that stores the 32 bit pc relative
+/* This is a 64 bit reloc that stores the 32 bit pc relative
value in two words (with an imm instruction). The relocation is
PC-relative offset into PLT */
BFD_RELOC_MICROBLAZE_64_PLT,
-/* This is a 64 bit reloc that stores the 32 bit GOT relative
+/* This is a 64 bit reloc that stores the 32 bit GOT relative
value in two words (with an imm instruction). The relocation is
relative offset from _GLOBAL_OFFSET_TABLE_ */
BFD_RELOC_MICROBLAZE_64_GOTOFF,
-/* This is a 32 bit reloc that stores the 32 bit GOT relative
+/* This is a 32 bit reloc that stores the 32 bit GOT relative
value in a word. The relocation is relative offset from */
BFD_RELOC_MICROBLAZE_32_GOTOFF,
the dynamic object into the runtime process image. */
BFD_RELOC_MICROBLAZE_COPY,
+/* Unused Reloc */
+ BFD_RELOC_MICROBLAZE_64_TLS,
+
+/* This is a 64 bit reloc that stores the 32 bit GOT relative value
+of the GOT TLS GD info entry in two words (with an imm instruction). The
+relocation is GOT offset. */
+ BFD_RELOC_MICROBLAZE_64_TLSGD,
+
+/* This is a 64 bit reloc that stores the 32 bit GOT relative value
+of the GOT TLS LD info entry in two words (with an imm instruction). The
+relocation is GOT offset. */
+ BFD_RELOC_MICROBLAZE_64_TLSLD,
+
+/* This is a 32 bit reloc that stores the Module ID to GOT(n). */
+ BFD_RELOC_MICROBLAZE_32_TLSDTPMOD,
+
+/* This is a 32 bit reloc that stores TLS offset to GOT(n+1). */
+ BFD_RELOC_MICROBLAZE_32_TLSDTPREL,
+
+/* This is a 32 bit reloc for storing TLS offset to two words (uses imm
+instruction) */
+ BFD_RELOC_MICROBLAZE_64_TLSDTPREL,
+
+/* This is a 64 bit reloc that stores 32-bit thread pointer relative offset
+to two words (uses imm instruction). */
+ BFD_RELOC_MICROBLAZE_64_TLSGOTTPREL,
+
+/* This is a 64 bit reloc that stores 32-bit thread pointer relative offset
+to two words (uses imm instruction). */
+ BFD_RELOC_MICROBLAZE_64_TLSTPREL,
+
+/* AArch64 ADD immediate instruction, holding bits 0 to 11 of the address.
+Used in conjunction with BFD_RELOC_AARCH64_ADR_HI21_PCREL. */
+ BFD_RELOC_AARCH64_ADD_LO12,
+
+/* AArch64 Load Literal instruction, holding a 19 bit PC relative word
+offset of the global offset table entry for a symbol. The lowest two
+bits must be zero and are not stored in the instruction, giving a 21
+bit signed byte offset. This relocation type requires signed overflow
+checking. */
+ BFD_RELOC_AARCH64_GOT_LD_PREL19,
+
+/* Get to the page base of the global offset table entry for a symbol as
+part of an ADRP instruction using a 21 bit PC relative value.Used in
+conjunction with BFD_RELOC_AARCH64_LD64_GOT_LO12_NC. */
+ BFD_RELOC_AARCH64_ADR_GOT_PAGE,
+
+/* AArch64 ADRP instruction, with bits 12 to 32 of a pc-relative page
+offset, giving a 4KB aligned page base address. */
+ BFD_RELOC_AARCH64_ADR_HI21_PCREL,
+
+/* AArch64 ADRP instruction, with bits 12 to 32 of a pc-relative page
+offset, giving a 4KB aligned page base address, but with no overflow
+checking. */
+ BFD_RELOC_AARCH64_ADR_HI21_NC_PCREL,
+
+/* AArch64 ADR instruction, holding a simple 21 bit pc-relative byte offset. */
+ BFD_RELOC_AARCH64_ADR_LO21_PCREL,
+
+/* AArch64 19 bit pc-relative conditional branch and compare & branch.
+The lowest two bits must be zero and are not stored in the instruction,
+giving a 21 bit signed byte offset. */
+ BFD_RELOC_AARCH64_BRANCH19,
+
+/* AArch64 26 bit pc-relative unconditional branch and link.
+The lowest two bits must be zero and are not stored in the instruction,
+giving a 28 bit signed byte offset. */
+ BFD_RELOC_AARCH64_CALL26,
+
+/* AArch64 pseudo relocation code to be used internally by the AArch64
+assembler and not (currently) written to any object files. */
+ BFD_RELOC_AARCH64_GAS_INTERNAL_FIXUP,
+
+/* AArch64 26 bit pc-relative unconditional branch.
+The lowest two bits must be zero and are not stored in the instruction,
+giving a 28 bit signed byte offset. */
+ BFD_RELOC_AARCH64_JUMP26,
+
+/* AArch64 Load Literal instruction, holding a 19 bit pc-relative word
+offset. The lowest two bits must be zero and are not stored in the
+instruction, giving a 21 bit signed byte offset. */
+ BFD_RELOC_AARCH64_LD_LO19_PCREL,
+
+/* Unsigned 12 bit byte offset for 64 bit load/store from the page of
+the GOT entry for this symbol. Used in conjunction with
+BFD_RELOC_AARCH64_ADR_GOTPAGE. */
+ BFD_RELOC_AARCH64_LD64_GOT_LO12_NC,
+
+/* AArch64 unspecified load/store instruction, holding bits 0 to 11 of the
+address. Used in conjunction with BFD_RELOC_AARCH64_ADR_HI21_PCREL. */
+ BFD_RELOC_AARCH64_LDST_LO12,
+
+/* AArch64 8-bit load/store instruction, holding bits 0 to 11 of the
+address. Used in conjunction with BFD_RELOC_AARCH64_ADR_HI21_PCREL. */
+ BFD_RELOC_AARCH64_LDST8_LO12,
+
+/* AArch64 16-bit load/store instruction, holding bits 0 to 11 of the
+address. Used in conjunction with BFD_RELOC_AARCH64_ADR_HI21_PCREL. */
+ BFD_RELOC_AARCH64_LDST16_LO12,
+
+/* AArch64 32-bit load/store instruction, holding bits 0 to 11 of the
+address. Used in conjunction with BFD_RELOC_AARCH64_ADR_HI21_PCREL. */
+ BFD_RELOC_AARCH64_LDST32_LO12,
+
+/* AArch64 64-bit load/store instruction, holding bits 0 to 11 of the
+address. Used in conjunction with BFD_RELOC_AARCH64_ADR_HI21_PCREL. */
+ BFD_RELOC_AARCH64_LDST64_LO12,
+
+/* AArch64 128-bit load/store instruction, holding bits 0 to 11 of the
+address. Used in conjunction with BFD_RELOC_AARCH64_ADR_HI21_PCREL. */
+ BFD_RELOC_AARCH64_LDST128_LO12,
+
+/* AArch64 MOV[NZK] instruction with most significant bits 0 to 15
+of an unsigned address/value. */
+ BFD_RELOC_AARCH64_MOVW_G0,
+
+/* AArch64 MOV[NZ] instruction with most significant bits 0 to 15
+of a signed value. Changes instruction to MOVZ or MOVN depending on the
+value's sign. */
+ BFD_RELOC_AARCH64_MOVW_G0_S,
+
+/* AArch64 MOV[NZK] instruction with less significant bits 0 to 15 of
+an address/value. No overflow checking. */
+ BFD_RELOC_AARCH64_MOVW_G0_NC,
+
+/* AArch64 MOV[NZK] instruction with most significant bits 16 to 31
+of an unsigned address/value. */
+ BFD_RELOC_AARCH64_MOVW_G1,
+
+/* AArch64 MOV[NZK] instruction with less significant bits 16 to 31
+of an address/value. No overflow checking. */
+ BFD_RELOC_AARCH64_MOVW_G1_NC,
+
+/* AArch64 MOV[NZ] instruction with most significant bits 16 to 31
+of a signed value. Changes instruction to MOVZ or MOVN depending on the
+value's sign. */
+ BFD_RELOC_AARCH64_MOVW_G1_S,
+
+/* AArch64 MOV[NZK] instruction with most significant bits 32 to 47
+of an unsigned address/value. */
+ BFD_RELOC_AARCH64_MOVW_G2,
+
+/* AArch64 MOV[NZK] instruction with less significant bits 32 to 47
+of an address/value. No overflow checking. */
+ BFD_RELOC_AARCH64_MOVW_G2_NC,
+
+/* AArch64 MOV[NZ] instruction with most significant bits 32 to 47
+of a signed value. Changes instruction to MOVZ or MOVN depending on the
+value's sign. */
+ BFD_RELOC_AARCH64_MOVW_G2_S,
+
+/* AArch64 MOV[NZK] instruction with most signficant bits 48 to 64
+of a signed or unsigned address/value. */
+ BFD_RELOC_AARCH64_MOVW_G3,
+
+/* AArch64 TLS relocation. */
+ BFD_RELOC_AARCH64_TLSDESC,
+
+/* AArch64 TLS DESC relocation. */
+ BFD_RELOC_AARCH64_TLSDESC_ADD,
+
+/* AArch64 TLS DESC relocation. */
+ BFD_RELOC_AARCH64_TLSDESC_ADD_LO12_NC,
+
+/* AArch64 TLS DESC relocation. */
+ BFD_RELOC_AARCH64_TLSDESC_ADR_PAGE,
+
+/* AArch64 TLS DESC relocation. */
+ BFD_RELOC_AARCH64_TLSDESC_ADR_PREL21,
+
+/* AArch64 TLS DESC relocation. */
+ BFD_RELOC_AARCH64_TLSDESC_CALL,
+
+/* AArch64 TLS DESC relocation. */
+ BFD_RELOC_AARCH64_TLSDESC_LD64_LO12_NC,
+
+/* AArch64 TLS DESC relocation. */
+ BFD_RELOC_AARCH64_TLSDESC_LD64_PREL19,
+
+/* AArch64 TLS DESC relocation. */
+ BFD_RELOC_AARCH64_TLSDESC_LDR,
+
+/* AArch64 TLS DESC relocation. */
+ BFD_RELOC_AARCH64_TLSDESC_OFF_G0_NC,
+
+/* AArch64 TLS DESC relocation. */
+ BFD_RELOC_AARCH64_TLSDESC_OFF_G1,
+
+/* Unsigned 12 bit byte offset to global offset table entry for a symbols
+tls_index structure. Used in conjunction with
+BFD_RELOC_AARCH64_TLSGD_ADR_PAGE21. */
+ BFD_RELOC_AARCH64_TLSGD_ADD_LO12_NC,
+
+/* Get to the page base of the global offset table entry for a symbols
+tls_index structure as part of an adrp instruction using a 21 bit PC
+relative value. Used in conjunction with
+BFD_RELOC_AARCH64_TLSGD_ADD_LO12_NC. */
+ BFD_RELOC_AARCH64_TLSGD_ADR_PAGE21,
+
+/* AArch64 TLS INITIAL EXEC relocation. */
+ BFD_RELOC_AARCH64_TLSIE_ADR_GOTTPREL_PAGE21,
+
+/* AArch64 TLS INITIAL EXEC relocation. */
+ BFD_RELOC_AARCH64_TLSIE_LD_GOTTPREL_PREL19,
+
+/* AArch64 TLS INITIAL EXEC relocation. */
+ BFD_RELOC_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC,
+
+/* AArch64 TLS INITIAL EXEC relocation. */
+ BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G0_NC,
+
+/* AArch64 TLS INITIAL EXEC relocation. */
+ BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G1,
+
+/* AArch64 TLS LOCAL EXEC relocation. */
+ BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_HI12,
+
+/* AArch64 TLS LOCAL EXEC relocation. */
+ BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12,
+
+/* AArch64 TLS LOCAL EXEC relocation. */
+ BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12_NC,
+
+/* AArch64 TLS LOCAL EXEC relocation. */
+ BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0,
+
+/* AArch64 TLS LOCAL EXEC relocation. */
+ BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0_NC,
+
+/* AArch64 TLS LOCAL EXEC relocation. */
+ BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1,
+
+/* AArch64 TLS LOCAL EXEC relocation. */
+ BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1_NC,
+
+/* AArch64 TLS LOCAL EXEC relocation. */
+ BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G2,
+
+/* AArch64 TLS relocation. */
+ BFD_RELOC_AARCH64_TLS_DTPMOD64,
+
+/* AArch64 TLS relocation. */
+ BFD_RELOC_AARCH64_TLS_DTPREL64,
+
+/* AArch64 TLS relocation. */
+ BFD_RELOC_AARCH64_TLS_TPREL64,
+
+/* AArch64 14 bit pc-relative test bit and branch.
+The lowest two bits must be zero and are not stored in the instruction,
+giving a 16 bit signed byte offset. */
+ BFD_RELOC_AARCH64_TSTBR14,
+
/* Tilera TILEPro Relocations. */
BFD_RELOC_TILEPRO_COPY,
BFD_RELOC_TILEPRO_GLOB_DAT,
BFD_RELOC_TILEPRO_SHAMT_X1,
BFD_RELOC_TILEPRO_SHAMT_Y0,
BFD_RELOC_TILEPRO_SHAMT_Y1,
+ BFD_RELOC_TILEPRO_TLS_GD_CALL,
+ BFD_RELOC_TILEPRO_IMM8_X0_TLS_GD_ADD,
+ BFD_RELOC_TILEPRO_IMM8_X1_TLS_GD_ADD,
+ BFD_RELOC_TILEPRO_IMM8_Y0_TLS_GD_ADD,
+ BFD_RELOC_TILEPRO_IMM8_Y1_TLS_GD_ADD,
+ BFD_RELOC_TILEPRO_TLS_IE_LOAD,
BFD_RELOC_TILEPRO_IMM16_X0_TLS_GD,
BFD_RELOC_TILEPRO_IMM16_X1_TLS_GD,
BFD_RELOC_TILEPRO_IMM16_X0_TLS_GD_LO,
BFD_RELOC_TILEPRO_TLS_DTPMOD32,
BFD_RELOC_TILEPRO_TLS_DTPOFF32,
BFD_RELOC_TILEPRO_TLS_TPOFF32,
+ BFD_RELOC_TILEPRO_IMM16_X0_TLS_LE,
+ BFD_RELOC_TILEPRO_IMM16_X1_TLS_LE,
+ BFD_RELOC_TILEPRO_IMM16_X0_TLS_LE_LO,
+ BFD_RELOC_TILEPRO_IMM16_X1_TLS_LE_LO,
+ BFD_RELOC_TILEPRO_IMM16_X0_TLS_LE_HI,
+ BFD_RELOC_TILEPRO_IMM16_X1_TLS_LE_HI,
+ BFD_RELOC_TILEPRO_IMM16_X0_TLS_LE_HA,
+ BFD_RELOC_TILEPRO_IMM16_X1_TLS_LE_HA,
/* Tilera TILE-Gx Relocations. */
BFD_RELOC_TILEGX_HW0,
BFD_RELOC_TILEGX_IMM16_X1_HW2_LAST_PCREL,
BFD_RELOC_TILEGX_IMM16_X0_HW0_GOT,
BFD_RELOC_TILEGX_IMM16_X1_HW0_GOT,
- BFD_RELOC_TILEGX_IMM16_X0_HW1_GOT,
- BFD_RELOC_TILEGX_IMM16_X1_HW1_GOT,
- BFD_RELOC_TILEGX_IMM16_X0_HW2_GOT,
- BFD_RELOC_TILEGX_IMM16_X1_HW2_GOT,
- BFD_RELOC_TILEGX_IMM16_X0_HW3_GOT,
- BFD_RELOC_TILEGX_IMM16_X1_HW3_GOT,
+ BFD_RELOC_TILEGX_IMM16_X0_HW0_PLT_PCREL,
+ BFD_RELOC_TILEGX_IMM16_X1_HW0_PLT_PCREL,
+ BFD_RELOC_TILEGX_IMM16_X0_HW1_PLT_PCREL,
+ BFD_RELOC_TILEGX_IMM16_X1_HW1_PLT_PCREL,
+ BFD_RELOC_TILEGX_IMM16_X0_HW2_PLT_PCREL,
+ BFD_RELOC_TILEGX_IMM16_X1_HW2_PLT_PCREL,
BFD_RELOC_TILEGX_IMM16_X0_HW0_LAST_GOT,
BFD_RELOC_TILEGX_IMM16_X1_HW0_LAST_GOT,
BFD_RELOC_TILEGX_IMM16_X0_HW1_LAST_GOT,
BFD_RELOC_TILEGX_IMM16_X1_HW1_LAST_GOT,
- BFD_RELOC_TILEGX_IMM16_X0_HW2_LAST_GOT,
- BFD_RELOC_TILEGX_IMM16_X1_HW2_LAST_GOT,
+ BFD_RELOC_TILEGX_IMM16_X0_HW3_PLT_PCREL,
+ BFD_RELOC_TILEGX_IMM16_X1_HW3_PLT_PCREL,
BFD_RELOC_TILEGX_IMM16_X0_HW0_TLS_GD,
BFD_RELOC_TILEGX_IMM16_X1_HW0_TLS_GD,
- BFD_RELOC_TILEGX_IMM16_X0_HW1_TLS_GD,
- BFD_RELOC_TILEGX_IMM16_X1_HW1_TLS_GD,
- BFD_RELOC_TILEGX_IMM16_X0_HW2_TLS_GD,
- BFD_RELOC_TILEGX_IMM16_X1_HW2_TLS_GD,
- BFD_RELOC_TILEGX_IMM16_X0_HW3_TLS_GD,
- BFD_RELOC_TILEGX_IMM16_X1_HW3_TLS_GD,
+ BFD_RELOC_TILEGX_IMM16_X0_HW0_TLS_LE,
+ BFD_RELOC_TILEGX_IMM16_X1_HW0_TLS_LE,
+ BFD_RELOC_TILEGX_IMM16_X0_HW0_LAST_TLS_LE,
+ BFD_RELOC_TILEGX_IMM16_X1_HW0_LAST_TLS_LE,
+ BFD_RELOC_TILEGX_IMM16_X0_HW1_LAST_TLS_LE,
+ BFD_RELOC_TILEGX_IMM16_X1_HW1_LAST_TLS_LE,
BFD_RELOC_TILEGX_IMM16_X0_HW0_LAST_TLS_GD,
BFD_RELOC_TILEGX_IMM16_X1_HW0_LAST_TLS_GD,
BFD_RELOC_TILEGX_IMM16_X0_HW1_LAST_TLS_GD,
BFD_RELOC_TILEGX_IMM16_X1_HW1_LAST_TLS_GD,
- BFD_RELOC_TILEGX_IMM16_X0_HW2_LAST_TLS_GD,
- BFD_RELOC_TILEGX_IMM16_X1_HW2_LAST_TLS_GD,
BFD_RELOC_TILEGX_IMM16_X0_HW0_TLS_IE,
BFD_RELOC_TILEGX_IMM16_X1_HW0_TLS_IE,
- BFD_RELOC_TILEGX_IMM16_X0_HW1_TLS_IE,
- BFD_RELOC_TILEGX_IMM16_X1_HW1_TLS_IE,
- BFD_RELOC_TILEGX_IMM16_X0_HW2_TLS_IE,
- BFD_RELOC_TILEGX_IMM16_X1_HW2_TLS_IE,
- BFD_RELOC_TILEGX_IMM16_X0_HW3_TLS_IE,
- BFD_RELOC_TILEGX_IMM16_X1_HW3_TLS_IE,
+ BFD_RELOC_TILEGX_IMM16_X0_HW0_LAST_PLT_PCREL,
+ BFD_RELOC_TILEGX_IMM16_X1_HW0_LAST_PLT_PCREL,
+ BFD_RELOC_TILEGX_IMM16_X0_HW1_LAST_PLT_PCREL,
+ BFD_RELOC_TILEGX_IMM16_X1_HW1_LAST_PLT_PCREL,
+ BFD_RELOC_TILEGX_IMM16_X0_HW2_LAST_PLT_PCREL,
+ BFD_RELOC_TILEGX_IMM16_X1_HW2_LAST_PLT_PCREL,
BFD_RELOC_TILEGX_IMM16_X0_HW0_LAST_TLS_IE,
BFD_RELOC_TILEGX_IMM16_X1_HW0_LAST_TLS_IE,
BFD_RELOC_TILEGX_IMM16_X0_HW1_LAST_TLS_IE,
BFD_RELOC_TILEGX_IMM16_X1_HW1_LAST_TLS_IE,
- BFD_RELOC_TILEGX_IMM16_X0_HW2_LAST_TLS_IE,
- BFD_RELOC_TILEGX_IMM16_X1_HW2_LAST_TLS_IE,
BFD_RELOC_TILEGX_TLS_DTPMOD64,
BFD_RELOC_TILEGX_TLS_DTPOFF64,
BFD_RELOC_TILEGX_TLS_TPOFF64,
BFD_RELOC_TILEGX_TLS_DTPMOD32,
BFD_RELOC_TILEGX_TLS_DTPOFF32,
BFD_RELOC_TILEGX_TLS_TPOFF32,
+ BFD_RELOC_TILEGX_TLS_GD_CALL,
+ BFD_RELOC_TILEGX_IMM8_X0_TLS_GD_ADD,
+ BFD_RELOC_TILEGX_IMM8_X1_TLS_GD_ADD,
+ BFD_RELOC_TILEGX_IMM8_Y0_TLS_GD_ADD,
+ BFD_RELOC_TILEGX_IMM8_Y1_TLS_GD_ADD,
+ BFD_RELOC_TILEGX_TLS_IE_LOAD,
+ BFD_RELOC_TILEGX_IMM8_X0_TLS_ADD,
+ BFD_RELOC_TILEGX_IMM8_X1_TLS_ADD,
+ BFD_RELOC_TILEGX_IMM8_Y0_TLS_ADD,
+ BFD_RELOC_TILEGX_IMM8_Y1_TLS_ADD,
+
+/* Adapteva EPIPHANY - 8 bit signed pc-relative displacement */
+ BFD_RELOC_EPIPHANY_SIMM8,
+
+/* Adapteva EPIPHANY - 24 bit signed pc-relative displacement */
+ BFD_RELOC_EPIPHANY_SIMM24,
+
+/* Adapteva EPIPHANY - 16 most-significant bits of absolute address */
+ BFD_RELOC_EPIPHANY_HIGH,
+
+/* Adapteva EPIPHANY - 16 least-significant bits of absolute address */
+ BFD_RELOC_EPIPHANY_LOW,
+
+/* Adapteva EPIPHANY - 11 bit signed number - add/sub immediate */
+ BFD_RELOC_EPIPHANY_SIMM11,
+
+/* Adapteva EPIPHANY - 11 bit sign-magnitude number (ld/st displacement) */
+ BFD_RELOC_EPIPHANY_IMM11,
+
+/* Adapteva EPIPHANY - 8 bit immediate for 16 bit mov instruction. */
+ BFD_RELOC_EPIPHANY_IMM8,
BFD_RELOC_UNUSED };
typedef enum bfd_reloc_code_real bfd_reloc_code_real_type;
reloc_howto_type *bfd_reloc_type_lookup
bfd_error_handler_type bfd_get_error_handler (void);
+typedef void (*bfd_assert_handler_type) (const char *bfd_formatmsg,
+ const char *bfd_version,
+ const char *bfd_file,
+ int bfd_line);
+
+bfd_assert_handler_type bfd_set_assert_handler (bfd_assert_handler_type);
+
+bfd_assert_handler_type bfd_get_assert_handler (void);
+
long bfd_get_reloc_upper_bound (bfd *abfd, asection *sect);
long bfd_canonicalize_reloc
BFD_SEND (abfd, _bfd_find_nearest_line, \
(abfd, sec, syms, off, file, func, line))
+#define bfd_find_nearest_line_discriminator(abfd, sec, syms, off, file, func, \
+ line, disc) \
+ BFD_SEND (abfd, _bfd_find_nearest_line_discriminator, \
+ (abfd, sec, syms, off, file, func, line, disc))
+
#define bfd_find_line(abfd, syms, sym, file, line) \
BFD_SEND (abfd, _bfd_find_line, \
(abfd, syms, sym, file, line))
#define bfd_gc_sections(abfd, link_info) \
BFD_SEND (abfd, _bfd_gc_sections, (abfd, link_info))
+#define bfd_lookup_section_flags(link_info, flag_info, section) \
+ BFD_SEND (abfd, _bfd_lookup_section_flags, (link_info, flag_info, section))
+
#define bfd_merge_sections(abfd, link_info) \
BFD_SEND (abfd, _bfd_merge_sections, (abfd, link_info))
bfd_boolean bfd_alt_mach_code (bfd *abfd, int alternative);
-struct bfd_preserve
-{
- void *marker;
- void *tdata;
- flagword flags;
- const struct bfd_arch_info *arch_info;
- struct bfd_section *sections;
- struct bfd_section *section_last;
- unsigned int section_count;
- struct bfd_hash_table section_htab;
-};
-
-bfd_boolean bfd_preserve_save (bfd *, struct bfd_preserve *);
-
-void bfd_preserve_restore (bfd *, struct bfd_preserve *);
-
-void bfd_preserve_finish (bfd *, struct bfd_preserve *);
-
bfd_vma bfd_emul_get_maxpagesize (const char *);
void bfd_emul_set_maxpagesize (const char *, bfd_vma);
/* Forward declaration. */
typedef struct bfd_link_info _bfd_link_info;
+/* Forward declaration. */
+typedef struct flag_info flag_info;
+
typedef struct bfd_target
{
/* Identifies the kind of target, e.g., SunOS4, Ultrix, etc. */
NAME##_bfd_is_target_special_symbol, \
NAME##_get_lineno, \
NAME##_find_nearest_line, \
+ _bfd_generic_find_nearest_line_discriminator, \
_bfd_generic_find_line, \
NAME##_find_inliner_info, \
NAME##_bfd_make_debug_symbol, \
bfd_boolean (*_bfd_find_nearest_line)
(bfd *, struct bfd_section *, struct bfd_symbol **, bfd_vma,
const char **, const char **, unsigned int *);
+ bfd_boolean (*_bfd_find_nearest_line_discriminator)
+ (bfd *, struct bfd_section *, struct bfd_symbol **, bfd_vma,
+ const char **, const char **, unsigned int *, unsigned int *);
bfd_boolean (*_bfd_find_line)
(bfd *, struct bfd_symbol **, struct bfd_symbol *,
const char **, unsigned int *);
NAME##_bfd_final_link, \
NAME##_bfd_link_split_section, \
NAME##_bfd_gc_sections, \
+ NAME##_bfd_lookup_section_flags, \
NAME##_bfd_merge_sections, \
NAME##_bfd_is_group_section, \
NAME##_bfd_discard_group, \
/* Remove sections that are not referenced from the output. */
bfd_boolean (*_bfd_gc_sections) (bfd *, struct bfd_link_info *);
+ /* Sets the bitmask of allowed and disallowed section flags. */
+ bfd_boolean (*_bfd_lookup_section_flags) (struct bfd_link_info *,
+ struct flag_info *,
+ asection *);
+
/* Attempt to merge SEC_MERGE sections. */
bfd_boolean (*_bfd_merge_sections) (bfd *, struct bfd_link_info *);
/* Check if SEC has been already linked during a reloceatable or
final link. */
- void (*_section_already_linked) (bfd *, struct bfd_section *,
- struct bfd_link_info *);
+ bfd_boolean (*_section_already_linked) (bfd *, asection *,
+ struct bfd_link_info *);
/* Define a common symbol. */
bfd_boolean (*_bfd_define_common_symbol) (bfd *, struct bfd_link_info *,
#define bfd_link_split_section(abfd, sec) \
BFD_SEND (abfd, _bfd_link_split_section, (abfd, sec))
-void bfd_section_already_linked (bfd *abfd, asection *sec,
+bfd_boolean bfd_section_already_linked (bfd *abfd,
+ asection *sec,
struct bfd_link_info *info);
#define bfd_section_already_linked(abfd, sec, info) \
(struct bfd_elf_version_tree *verdefs,
const char *sym_name, bfd_boolean *hide);
+bfd_boolean bfd_hide_sym_by_version
+ (struct bfd_elf_version_tree *verdefs, const char *sym_name);
+
/* Extracted from simple.c. */
bfd_byte *bfd_simple_get_relocated_section_contents
(bfd *abfd, asection *sec, bfd_byte *outbuf, asymbol **symbol_table);
bfd_boolean bfd_get_full_section_contents
(bfd *abfd, asection *section, bfd_byte **ptr);
+void bfd_cache_section_contents
+ (asection *sec, void *contents);
+
bfd_boolean bfd_is_section_compressed
(bfd *abfd, asection *section);
projects / deliverable / binutils-gdb.git / blobdiff