Merge branch 'master' into merge-job

[deliverable/binutils-gdb.git] / bfd / bfd-in2.h

diff --git a/bfd/bfd-in2.h b/bfd/bfd-in2.h
index c6a58018dc141f390d0162d09a33bd7c8dfb7e1c..8323650164b3449aadb7bc7a9188f61de6fb6214 100644 (file)
--- a/bfd/bfd-in2.h
+++ b/bfd/bfd-in2.h
@@ -7,7 +7,8 @@
 
 /* Main header file for the bfd library -- portable access to object files.
 
-   Copyright (C) 1990-2019 Free Software Foundation, Inc.
+   Copyright (C) 1990-2020 Free Software Foundation, Inc.
+   Copyright (C) 2019-2020 Advanced Micro Devices, Inc. All rights reserved.
 
    Contributed by Cygnus Support.
 
@@ -1888,9 +1889,13 @@ enum bfd_architecture
   bfd_arch_xtensa,    /* Tensilica's Xtensa cores.  */
 #define bfd_mach_xtensa        1
   bfd_arch_z80,
-#define bfd_mach_z80strict     1 /* No undocumented opcodes.  */
-#define bfd_mach_z80           3 /* With ixl, ixh, iyl, and iyh.  */
-#define bfd_mach_z80full       7 /* All undocumented instructions.  */
+#define bfd_mach_gbz80         0 /* GameBoy Z80 (reduced instruction set) */
+#define bfd_mach_z80strict     1 /* Z80 without undocumented opcodes.  */
+#define bfd_mach_z180          2 /* Z180: successor with additional instructions, but without halves of ix and iy */
+#define bfd_mach_z80           3 /* Z80 with ixl, ixh, iyl, and iyh.  */
+#define bfd_mach_ez80_z80      4 /* eZ80 (successor of Z80 & Z180) in Z80 (16-bit address) mode */
+#define bfd_mach_ez80_adl      5 /* eZ80 (successor of Z80 & Z180) in ADL (24-bit address) mode */
+#define bfd_mach_z80full       7 /* Z80 with all undocumented instructions.  */
 #define bfd_mach_r800          11 /* R800: successor with multiplication.  */
   bfd_arch_lm32,      /* Lattice Mico32.  */
 #define bfd_mach_lm32          1
@@ -1925,6 +1930,18 @@ enum bfd_architecture
 #define bfd_mach_ck803         5
 #define bfd_mach_ck807         6
 #define bfd_mach_ck810         7
+  bfd_arch_amdgcn,     /* AMD GPU Architecture. Must match EF_AMDGPU_MACH_* */
+#define bfd_mach_amdgcn_unknown 0x000
+#define bfd_mach_amdgcn_gfx801  0x028
+#define bfd_mach_amdgcn_gfx802  0x029
+#define bfd_mach_amdgcn_gfx803  0x02a
+#define bfd_mach_amdgcn_gfx810  0x02b
+#define bfd_mach_amdgcn_gfx900  0x02c
+#define bfd_mach_amdgcn_gfx902  0x02d
+#define bfd_mach_amdgcn_gfx904  0x02e
+#define bfd_mach_amdgcn_gfx906  0x02f
+#define bfd_mach_amdgcn_gfx908  0x030
+#define bfd_mach_amdgcn_gfx909  0x031
   bfd_arch_last
   };
 
@@ -5270,6 +5287,24 @@ BFD_RELOC_XTENSA_ASM_EXPAND.  */
 /* 8 bit signed offset in (ix+d) or (iy+d).  */
   BFD_RELOC_Z80_DISP8,
 
+/* First 8 bits of multibyte (32, 24 or 16 bit) value.  */
+  BFD_RELOC_Z80_BYTE0,
+
+/* Second 8 bits of multibyte (32, 24 or 16 bit) value.  */
+  BFD_RELOC_Z80_BYTE1,
+
+/* Third 8 bits of multibyte (32 or 24 bit) value.  */
+  BFD_RELOC_Z80_BYTE2,
+
+/* Fourth 8 bits of multibyte (32 bit) value.  */
+  BFD_RELOC_Z80_BYTE3,
+
+/* Lowest 16 bits of multibyte (32 or 24 bit) value.  */
+  BFD_RELOC_Z80_WORD0,
+
+/* Highest 16 bits of multibyte (32 or 24 bit) value.  */
+  BFD_RELOC_Z80_WORD1,
+
 /* DJNZ offset.  */
   BFD_RELOC_Z8K_DISP7,