to two words (uses imm instruction). */
BFD_RELOC_MICROBLAZE_64_TLSTPREL,
-/* AArch64 ADD immediate instruction, holding bits 0 to 11 of the address.
-Used in conjunction with BFD_RELOC_AARCH64_ADR_HI21_PCREL. */
- BFD_RELOC_AARCH64_ADD_LO12,
+/* AArch64 pseudo relocation code to mark the start of the AArch64
+relocation enumerators. N.B. the order of the enumerators is
+important as several tables in the AArch64 bfd backend are indexed
+by these enumerators; make sure they are all synced. */
+ BFD_RELOC_AARCH64_RELOC_START,
+
+/* AArch64 null relocation code. */
+ BFD_RELOC_AARCH64_NONE,
+
+/* Basic absolute relocations of N bits. These are equivalent to
+BFD_RELOC_N and they were added to assist the indexing of the howto
+table. */
+ BFD_RELOC_AARCH64_64,
+ BFD_RELOC_AARCH64_32,
+ BFD_RELOC_AARCH64_16,
+
+/* PC-relative relocations. These are equivalent to BFD_RELOC_N_PCREL
+and they were added to assist the indexing of the howto table. */
+ BFD_RELOC_AARCH64_64_PCREL,
+ BFD_RELOC_AARCH64_32_PCREL,
+ BFD_RELOC_AARCH64_16_PCREL,
-/* AArch64 Load Literal instruction, holding a 19 bit PC relative word
-offset of the global offset table entry for a symbol. The lowest two
-bits must be zero and are not stored in the instruction, giving a 21
-bit signed byte offset. This relocation type requires signed overflow
-checking. */
- BFD_RELOC_AARCH64_GOT_LD_PREL19,
+/* AArch64 MOV[NZK] instruction with most significant bits 0 to 15
+of an unsigned address/value. */
+ BFD_RELOC_AARCH64_MOVW_G0,
-/* Get to the page base of the global offset table entry for a symbol as
-part of an ADRP instruction using a 21 bit PC relative value.Used in
-conjunction with BFD_RELOC_AARCH64_LD64_GOT_LO12_NC. */
- BFD_RELOC_AARCH64_ADR_GOT_PAGE,
+/* AArch64 MOV[NZK] instruction with less significant bits 0 to 15 of
+an address/value. No overflow checking. */
+ BFD_RELOC_AARCH64_MOVW_G0_NC,
+
+/* AArch64 MOV[NZK] instruction with most significant bits 16 to 31
+of an unsigned address/value. */
+ BFD_RELOC_AARCH64_MOVW_G1,
+
+/* AArch64 MOV[NZK] instruction with less significant bits 16 to 31
+of an address/value. No overflow checking. */
+ BFD_RELOC_AARCH64_MOVW_G1_NC,
+
+/* AArch64 MOV[NZK] instruction with most significant bits 32 to 47
+of an unsigned address/value. */
+ BFD_RELOC_AARCH64_MOVW_G2,
+
+/* AArch64 MOV[NZK] instruction with less significant bits 32 to 47
+of an address/value. No overflow checking. */
+ BFD_RELOC_AARCH64_MOVW_G2_NC,
+
+/* AArch64 MOV[NZK] instruction with most signficant bits 48 to 64
+of a signed or unsigned address/value. */
+ BFD_RELOC_AARCH64_MOVW_G3,
+
+/* AArch64 MOV[NZ] instruction with most significant bits 0 to 15
+of a signed value. Changes instruction to MOVZ or MOVN depending on the
+value's sign. */
+ BFD_RELOC_AARCH64_MOVW_G0_S,
+
+/* AArch64 MOV[NZ] instruction with most significant bits 16 to 31
+of a signed value. Changes instruction to MOVZ or MOVN depending on the
+value's sign. */
+ BFD_RELOC_AARCH64_MOVW_G1_S,
+
+/* AArch64 MOV[NZ] instruction with most significant bits 32 to 47
+of a signed value. Changes instruction to MOVZ or MOVN depending on the
+value's sign. */
+ BFD_RELOC_AARCH64_MOVW_G2_S,
+
+/* AArch64 Load Literal instruction, holding a 19 bit pc-relative word
+offset. The lowest two bits must be zero and are not stored in the
+instruction, giving a 21 bit signed byte offset. */
+ BFD_RELOC_AARCH64_LD_LO19_PCREL,
+
+/* AArch64 ADR instruction, holding a simple 21 bit pc-relative byte offset. */
+ BFD_RELOC_AARCH64_ADR_LO21_PCREL,
/* AArch64 ADRP instruction, with bits 12 to 32 of a pc-relative page
offset, giving a 4KB aligned page base address. */
checking. */
BFD_RELOC_AARCH64_ADR_HI21_NC_PCREL,
-/* AArch64 ADR instruction, holding a simple 21 bit pc-relative byte offset. */
- BFD_RELOC_AARCH64_ADR_LO21_PCREL,
+/* AArch64 ADD immediate instruction, holding bits 0 to 11 of the address.
+Used in conjunction with BFD_RELOC_AARCH64_ADR_HI21_PCREL. */
+ BFD_RELOC_AARCH64_ADD_LO12,
+
+/* AArch64 8-bit load/store instruction, holding bits 0 to 11 of the
+address. Used in conjunction with BFD_RELOC_AARCH64_ADR_HI21_PCREL. */
+ BFD_RELOC_AARCH64_LDST8_LO12,
+
+/* AArch64 14 bit pc-relative test bit and branch.
+The lowest two bits must be zero and are not stored in the instruction,
+giving a 16 bit signed byte offset. */
+ BFD_RELOC_AARCH64_TSTBR14,
/* AArch64 19 bit pc-relative conditional branch and compare & branch.
The lowest two bits must be zero and are not stored in the instruction,
giving a 21 bit signed byte offset. */
BFD_RELOC_AARCH64_BRANCH19,
-/* AArch64 26 bit pc-relative unconditional branch and link.
-The lowest two bits must be zero and are not stored in the instruction,
-giving a 28 bit signed byte offset. */
- BFD_RELOC_AARCH64_CALL26,
-
-/* AArch64 pseudo relocation code to be used internally by the AArch64
-assembler and not (currently) written to any object files. */
- BFD_RELOC_AARCH64_GAS_INTERNAL_FIXUP,
-
/* AArch64 26 bit pc-relative unconditional branch.
The lowest two bits must be zero and are not stored in the instruction,
giving a 28 bit signed byte offset. */
BFD_RELOC_AARCH64_JUMP26,
-/* AArch64 Load Literal instruction, holding a 19 bit pc-relative word
-offset. The lowest two bits must be zero and are not stored in the
-instruction, giving a 21 bit signed byte offset. */
- BFD_RELOC_AARCH64_LD_LO19_PCREL,
-
-/* Unsigned 12 bit byte offset for 64 bit load/store from the page of
-the GOT entry for this symbol. Used in conjunction with
-BFD_RELOC_AARCH64_ADR_GOTPAGE. */
- BFD_RELOC_AARCH64_LD64_GOT_LO12_NC,
-
-/* AArch64 unspecified load/store instruction, holding bits 0 to 11 of the
-address. Used in conjunction with BFD_RELOC_AARCH64_ADR_HI21_PCREL. */
- BFD_RELOC_AARCH64_LDST_LO12,
-
-/* AArch64 8-bit load/store instruction, holding bits 0 to 11 of the
-address. Used in conjunction with BFD_RELOC_AARCH64_ADR_HI21_PCREL. */
- BFD_RELOC_AARCH64_LDST8_LO12,
+/* AArch64 26 bit pc-relative unconditional branch and link.
+The lowest two bits must be zero and are not stored in the instruction,
+giving a 28 bit signed byte offset. */
+ BFD_RELOC_AARCH64_CALL26,
/* AArch64 16-bit load/store instruction, holding bits 0 to 11 of the
address. Used in conjunction with BFD_RELOC_AARCH64_ADR_HI21_PCREL. */
address. Used in conjunction with BFD_RELOC_AARCH64_ADR_HI21_PCREL. */
BFD_RELOC_AARCH64_LDST128_LO12,
-/* AArch64 MOV[NZK] instruction with most significant bits 0 to 15
-of an unsigned address/value. */
- BFD_RELOC_AARCH64_MOVW_G0,
+/* AArch64 Load Literal instruction, holding a 19 bit PC relative word
+offset of the global offset table entry for a symbol. The lowest two
+bits must be zero and are not stored in the instruction, giving a 21
+bit signed byte offset. This relocation type requires signed overflow
+checking. */
+ BFD_RELOC_AARCH64_GOT_LD_PREL19,
-/* AArch64 MOV[NZ] instruction with most significant bits 0 to 15
-of a signed value. Changes instruction to MOVZ or MOVN depending on the
-value's sign. */
- BFD_RELOC_AARCH64_MOVW_G0_S,
+/* Get to the page base of the global offset table entry for a symbol as
+part of an ADRP instruction using a 21 bit PC relative value.Used in
+conjunction with BFD_RELOC_AARCH64_LD64_GOT_LO12_NC. */
+ BFD_RELOC_AARCH64_ADR_GOT_PAGE,
-/* AArch64 MOV[NZK] instruction with less significant bits 0 to 15 of
-an address/value. No overflow checking. */
- BFD_RELOC_AARCH64_MOVW_G0_NC,
+/* Unsigned 12 bit byte offset for 64 bit load/store from the page of
+the GOT entry for this symbol. Used in conjunction with
+BFD_RELOC_AARCH64_ADR_GOTPAGE. Valid in LP64 ABI only. */
+ BFD_RELOC_AARCH64_LD64_GOT_LO12_NC,
-/* AArch64 MOV[NZK] instruction with most significant bits 16 to 31
-of an unsigned address/value. */
- BFD_RELOC_AARCH64_MOVW_G1,
+/* Unsigned 12 bit byte offset for 32 bit load/store from the page of
+the GOT entry for this symbol. Used in conjunction with
+BFD_RELOC_AARCH64_ADR_GOTPAGE. Valid in ILP32 ABI only. */
+ BFD_RELOC_AARCH64_LD32_GOT_LO12_NC,
-/* AArch64 MOV[NZK] instruction with less significant bits 16 to 31
-of an address/value. No overflow checking. */
- BFD_RELOC_AARCH64_MOVW_G1_NC,
+/* Get to the page base of the global offset table entry for a symbols
+tls_index structure as part of an adrp instruction using a 21 bit PC
+relative value. Used in conjunction with
+BFD_RELOC_AARCH64_TLSGD_ADD_LO12_NC. */
+ BFD_RELOC_AARCH64_TLSGD_ADR_PAGE21,
-/* AArch64 MOV[NZ] instruction with most significant bits 16 to 31
-of a signed value. Changes instruction to MOVZ or MOVN depending on the
-value's sign. */
- BFD_RELOC_AARCH64_MOVW_G1_S,
+/* Unsigned 12 bit byte offset to global offset table entry for a symbols
+tls_index structure. Used in conjunction with
+BFD_RELOC_AARCH64_TLSGD_ADR_PAGE21. */
+ BFD_RELOC_AARCH64_TLSGD_ADD_LO12_NC,
-/* AArch64 MOV[NZK] instruction with most significant bits 32 to 47
-of an unsigned address/value. */
- BFD_RELOC_AARCH64_MOVW_G2,
+/* AArch64 TLS INITIAL EXEC relocation. */
+ BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G1,
-/* AArch64 MOV[NZK] instruction with less significant bits 32 to 47
-of an address/value. No overflow checking. */
- BFD_RELOC_AARCH64_MOVW_G2_NC,
+/* AArch64 TLS INITIAL EXEC relocation. */
+ BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G0_NC,
-/* AArch64 MOV[NZ] instruction with most significant bits 32 to 47
-of a signed value. Changes instruction to MOVZ or MOVN depending on the
-value's sign. */
- BFD_RELOC_AARCH64_MOVW_G2_S,
+/* AArch64 TLS INITIAL EXEC relocation. */
+ BFD_RELOC_AARCH64_TLSIE_ADR_GOTTPREL_PAGE21,
-/* AArch64 MOV[NZK] instruction with most signficant bits 48 to 64
-of a signed or unsigned address/value. */
- BFD_RELOC_AARCH64_MOVW_G3,
+/* AArch64 TLS INITIAL EXEC relocation. */
+ BFD_RELOC_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC,
-/* AArch64 TLS relocation. */
- BFD_RELOC_AARCH64_TLSDESC,
+/* AArch64 TLS INITIAL EXEC relocation. */
+ BFD_RELOC_AARCH64_TLSIE_LD32_GOTTPREL_LO12_NC,
-/* AArch64 TLS DESC relocation. */
- BFD_RELOC_AARCH64_TLSDESC_ADD,
+/* AArch64 TLS INITIAL EXEC relocation. */
+ BFD_RELOC_AARCH64_TLSIE_LD_GOTTPREL_PREL19,
-/* AArch64 TLS DESC relocation. */
- BFD_RELOC_AARCH64_TLSDESC_ADD_LO12_NC,
+/* AArch64 TLS LOCAL EXEC relocation. */
+ BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G2,
+
+/* AArch64 TLS LOCAL EXEC relocation. */
+ BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1,
+
+/* AArch64 TLS LOCAL EXEC relocation. */
+ BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1_NC,
+
+/* AArch64 TLS LOCAL EXEC relocation. */
+ BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0,
+
+/* AArch64 TLS LOCAL EXEC relocation. */
+ BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0_NC,
+
+/* AArch64 TLS LOCAL EXEC relocation. */
+ BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_HI12,
+
+/* AArch64 TLS LOCAL EXEC relocation. */
+ BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12,
+
+/* AArch64 TLS LOCAL EXEC relocation. */
+ BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12_NC,
/* AArch64 TLS DESC relocation. */
- BFD_RELOC_AARCH64_TLSDESC_ADR_PAGE21,
+ BFD_RELOC_AARCH64_TLSDESC_LD_PREL19,
/* AArch64 TLS DESC relocation. */
BFD_RELOC_AARCH64_TLSDESC_ADR_PREL21,
/* AArch64 TLS DESC relocation. */
- BFD_RELOC_AARCH64_TLSDESC_CALL,
+ BFD_RELOC_AARCH64_TLSDESC_ADR_PAGE21,
/* AArch64 TLS DESC relocation. */
BFD_RELOC_AARCH64_TLSDESC_LD64_LO12_NC,
/* AArch64 TLS DESC relocation. */
- BFD_RELOC_AARCH64_TLSDESC_LD_PREL19,
-
-/* AArch64 TLS DESC relocation. */
- BFD_RELOC_AARCH64_TLSDESC_LDR,
+ BFD_RELOC_AARCH64_TLSDESC_LD32_LO12_NC,
/* AArch64 TLS DESC relocation. */
- BFD_RELOC_AARCH64_TLSDESC_OFF_G0_NC,
+ BFD_RELOC_AARCH64_TLSDESC_ADD_LO12_NC,
/* AArch64 TLS DESC relocation. */
BFD_RELOC_AARCH64_TLSDESC_OFF_G1,
-/* Unsigned 12 bit byte offset to global offset table entry for a symbols
-tls_index structure. Used in conjunction with
-BFD_RELOC_AARCH64_TLSGD_ADR_PAGE21. */
- BFD_RELOC_AARCH64_TLSGD_ADD_LO12_NC,
+/* AArch64 TLS DESC relocation. */
+ BFD_RELOC_AARCH64_TLSDESC_OFF_G0_NC,
-/* Get to the page base of the global offset table entry for a symbols
-tls_index structure as part of an adrp instruction using a 21 bit PC
-relative value. Used in conjunction with
-BFD_RELOC_AARCH64_TLSGD_ADD_LO12_NC. */
- BFD_RELOC_AARCH64_TLSGD_ADR_PAGE21,
+/* AArch64 TLS DESC relocation. */
+ BFD_RELOC_AARCH64_TLSDESC_LDR,
-/* AArch64 TLS INITIAL EXEC relocation. */
- BFD_RELOC_AARCH64_TLSIE_ADR_GOTTPREL_PAGE21,
+/* AArch64 TLS DESC relocation. */
+ BFD_RELOC_AARCH64_TLSDESC_ADD,
-/* AArch64 TLS INITIAL EXEC relocation. */
- BFD_RELOC_AARCH64_TLSIE_LD_GOTTPREL_PREL19,
+/* AArch64 TLS DESC relocation. */
+ BFD_RELOC_AARCH64_TLSDESC_CALL,
-/* AArch64 TLS INITIAL EXEC relocation. */
- BFD_RELOC_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC,
+/* AArch64 TLS relocation. */
+ BFD_RELOC_AARCH64_COPY,
-/* AArch64 TLS INITIAL EXEC relocation. */
- BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G0_NC,
+/* AArch64 TLS relocation. */
+ BFD_RELOC_AARCH64_GLOB_DAT,
-/* AArch64 TLS INITIAL EXEC relocation. */
- BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G1,
+/* AArch64 TLS relocation. */
+ BFD_RELOC_AARCH64_JUMP_SLOT,
-/* AArch64 TLS LOCAL EXEC relocation. */
- BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_HI12,
+/* AArch64 TLS relocation. */
+ BFD_RELOC_AARCH64_RELATIVE,
-/* AArch64 TLS LOCAL EXEC relocation. */
- BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12,
+/* AArch64 TLS relocation. */
+ BFD_RELOC_AARCH64_TLS_DTPMOD,
-/* AArch64 TLS LOCAL EXEC relocation. */
- BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12_NC,
+/* AArch64 TLS relocation. */
+ BFD_RELOC_AARCH64_TLS_DTPREL,
-/* AArch64 TLS LOCAL EXEC relocation. */
- BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0,
+/* AArch64 TLS relocation. */
+ BFD_RELOC_AARCH64_TLS_TPREL,
-/* AArch64 TLS LOCAL EXEC relocation. */
- BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0_NC,
+/* AArch64 TLS relocation. */
+ BFD_RELOC_AARCH64_TLSDESC,
-/* AArch64 TLS LOCAL EXEC relocation. */
- BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1,
+/* AArch64 support for STT_GNU_IFUNC. */
+ BFD_RELOC_AARCH64_IRELATIVE,
-/* AArch64 TLS LOCAL EXEC relocation. */
- BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1_NC,
+/* AArch64 pseudo relocation code to mark the end of the AArch64
+relocation enumerators that have direct mapping to ELF reloc codes.
+There are a few more enumerators after this one; those are mainly
+used by the AArch64 assembler for the internal fixup or to select
+one of the above enumerators. */
+ BFD_RELOC_AARCH64_RELOC_END,
-/* AArch64 TLS LOCAL EXEC relocation. */
- BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G2,
+/* AArch64 pseudo relocation code to be used internally by the AArch64
+assembler and not (currently) written to any object files. */
+ BFD_RELOC_AARCH64_GAS_INTERNAL_FIXUP,
-/* AArch64 TLS relocation. */
- BFD_RELOC_AARCH64_TLS_DTPMOD64,
+/* AArch64 unspecified load/store instruction, holding bits 0 to 11 of the
+address. Used in conjunction with BFD_RELOC_AARCH64_ADR_HI21_PCREL. */
+ BFD_RELOC_AARCH64_LDST_LO12,
-/* AArch64 TLS relocation. */
- BFD_RELOC_AARCH64_TLS_DTPREL64,
+/* AArch64 pseudo relocation code to be used internally by the AArch64
+assembler and not (currently) written to any object files. */
+ BFD_RELOC_AARCH64_LD_GOT_LO12_NC,
-/* AArch64 TLS relocation. */
- BFD_RELOC_AARCH64_TLS_TPREL64,
+/* AArch64 pseudo relocation code to be used internally by the AArch64
+assembler and not (currently) written to any object files. */
+ BFD_RELOC_AARCH64_TLSIE_LD_GOTTPREL_LO12_NC,
-/* AArch64 14 bit pc-relative test bit and branch.
-The lowest two bits must be zero and are not stored in the instruction,
-giving a 16 bit signed byte offset. */
- BFD_RELOC_AARCH64_TSTBR14,
+/* AArch64 pseudo relocation code to be used internally by the AArch64
+assembler and not (currently) written to any object files. */
+ BFD_RELOC_AARCH64_TLSDESC_LD_LO12_NC,
/* Tilera TILEPro Relocations. */
BFD_RELOC_TILEPRO_COPY,
projects / deliverable / binutils-gdb.git / blobdiff