Merge branch 'master' into merge-job

[deliverable/binutils-gdb.git] / bfd / configure.ac

diff --git a/bfd/configure.ac b/bfd/configure.ac
index 7eee83ae4d4c9456c7b99d03a1bff905729f23c1..bf8106b856c0af61cfe30b3b1be342cb0432824b 100644 (file)
--- a/bfd/configure.ac
+++ b/bfd/configure.ac
@@ -1,6 +1,7 @@
 dnl Process this file with autoconf to produce a configure script.
 dnl
-dnl   Copyright (C) 2012-2019 Free Software Foundation, Inc.
+dnl   Copyright (C) 2012-2020 Free Software Foundation, Inc.
+dnl   Copyright (C) 2019-2020 Advanced Micro Devices, Inc. All rights reserved.
 dnl
 dnl This file is free software; you can redistribute it and/or modify
 dnl it under the terms of the GNU General Public License as published by
@@ -430,6 +431,7 @@ do
     alpha_vms_vec)              tb="$tb vms-alpha.lo vms-misc.lo vms-lib.lo"; target_size=64 ;;
     alpha_vms_lib_txt_vec)      tb="$tb vms-lib.lo vms-misc.lo" ;;
     am33_elf32_linux_vec)       tb="$tb elf32-am33lin.lo elf32.lo $elf" ;;
+    amdgcn_elf64_le_vec)        tb="$tb elf64-amdgcn.lo elf64.lo $elf"; target_size=64 ;;
     aout0_be_vec)               tb="$tb aout0.lo aout32.lo" ;;
     aout64_vec)                         tb="$tb demo64.lo aout64.lo"; target_size=64 ;;
     aout_vec)                   tb="$tb host-aout.lo aout32.lo" ;;
@@ -659,7 +661,6 @@ do
     tic6x_elf32_c6000_le_vec)   tb="$tb elf32-tic6x.lo elf32.lo $elf" ;;
     tic6x_elf32_linux_be_vec)   tb="$tb elf32-tic6x.lo elf32.lo $elf" ;;
     tic6x_elf32_linux_le_vec)   tb="$tb elf32-tic6x.lo elf32.lo $elf" ;;
-    tic80_coff_vec)             tb="$tb coff-tic80.lo $coff" ;;
     tilegx_elf32_be_vec)        tb="$tb elf32-tilegx.lo elfxx-tilegx.lo elf32.lo $elf" ; target_size=32 ;;
     tilegx_elf32_le_vec)        tb="$tb elf32-tilegx.lo elfxx-tilegx.lo elf32.lo $elf" ; target_size=32 ;;
     tilegx_elf64_be_vec)        tb="$tb elf64-tilegx.lo elfxx-tilegx.lo elf64.lo $elf" ; target_size=64 ;;
@@ -692,6 +693,7 @@ do
     xtensa_elf32_be_vec)        tb="$tb xtensa-isa.lo xtensa-modules.lo elf32-xtensa.lo elf32.lo $elf" ;;
     xtensa_elf32_le_vec)        tb="$tb xtensa-isa.lo xtensa-modules.lo elf32-xtensa.lo elf32.lo $elf" ;;
     z80_coff_vec)               tb="$tb coff-z80.lo reloc16.lo $coffgen" ;;
+    z80_elf32_vec)              tb="$tb elf32-z80.lo elf32.lo $elf" ;;
     z8k_coff_vec)               tb="$tb coff-z8k.lo reloc16.lo $coff" ;;
 
     # These appear out of order in targets.c